Date: Thursday 30 March 2017
Time: 15:30 - 16:00
Location / Room: IP sessions (in front of rooms 4A and 5A)

Interactive Presentations run simultaneously during a 30-minute slot. A poster associated to the IP paper is on display throughout the morning. Additionally, each IP paper is briefly introduced in a one-minute presentation in a corresponding regular session, prior to the actual Interactive Presentation. At the end of each afternoon Interactive Presentations session the award 'Best IP of the Day' is given.

Label	Presentation Title Authors
IP5-1	FORMAL MODEL FOR SYSTEM-LEVEL POWER MANAGEMENT DESIGN Speaker: Mirela Simonovic, Aggios, RS Authors: Mirela Simonovic1, Vojin Zivojnovic2 and Lazar Saranovac3 1University of Belgrade, RS; 2AGGIOS Inc., US; 3University of Belgrade, School of Electrical Engineering, RS Abstract In this paper we present a new formal model, called p-FSM, for system-level power management design. The p-FSM is a modular, compositional, hierarchical, and unified model for hardware and software components. The model encapsulates power management control mechanisms, operating states and properties of a component that affect power, energy and thermal aspects of the system. Inter-component dependencies are modeled through a component-based interface. By connecting multiple p-FSMs we gradually compose the model of the whole system which ensures correct-by-construction system-level control sequencing. The model can also be used to formally verify the functional correctness of the power management design. Download Paper (PDF; Only available from the DATE venue WiFi)
IP5-2	EXTENDING MEMORY CAPACITY OF NEURAL ASSOCIATIVE MEMORY BASED ON RECURSIVE SYNAPTIC BIT REUSE Speaker: Tianchan Guan, Columbia University, US Authors: Tianchan Guan1, Xiaoyang Zeng1 and Mingoo Seok2 1Fudan University, CN; 2Columbia University, US Abstract Neural associative memory (AM) is one of the critical building blocks for cognitive workloads such as classification and recognition. It learns and retrieves memories as humans brain does, i.e., changing the strengths of plastic synapses (weights) based on inputs and retrieving information by information itself. One of the key challenges in designing AM is to extend memory capacity (i.e., memories that a neural AM can learn) while minimizing power and hardware overhead. However, prior arts show that memory capacity scales slowly, often logarithmically or in squire root with the total bits of synaptic weights. This makes it prohibitive in hardware and power to achieve large memory capacity for practical applications. In this paper, we propose a synaptic model called recursive synaptic bit reuse, which enables near-linear scaling of memory capacity with total synaptic bits. Also, our model can handle input data that are correlated, more robustly than the conventional model. We experiment our proposed model in Hopfield Neural Networks (HNN) which contains the total synaptic bits of 5kB to 327kB and find that our model can increase the memory capacity as large as 30X over conventional models. We also study hardware cost via VLSI implementation of HNNs in a 65nm CMOS, confirming that our proposed model can achieve up to 10X area savings at the same capacity over conventional synaptic model. Download Paper (PDF; Only available from the DATE venue WiFi)
IP5-3	ANOMALIES IN SCHEDULING CONTROL APPLICATIONS AND DESIGN COMPLEXITY Speaker: Amir Aminifar, Swiss Federal Institute of Technology in Lausanne, CH Authors: Amir Aminifar1 and Enrico Bini2 1Swiss Federal Institute of Technology in Lausanne (EPFL), CH; 2University of Turin, IT Abstract Today, many control applications in cyber-physical systems are implemented on shared platforms. Such resource sharing may lead to complex timing behaviors and, in turn, instability of control applications. This paper highlights a number of anomalies demonstrating complex timing behaviors caused as a result of resource sharing. Such anomalous scenarios, then, lead to a dramatic increase in design complexity, if not properly considered. Here, we demonstrate that these anomalies are, in fact, very improbable. Therefore, design methodologies for these systems should mainly be devised and tuned towards the majority of cases, as opposed to anomalies, but should also be able to handle such anomalous scenarios. Download Paper (PDF; Only available from the DATE venue WiFi)
IP5-4	CONTRACT-BASED INTEGRATION OF AUTOMOTIVE CONTROL SOFTWARE Speaker: Tobias Sehnke, IAV GmbH, DE Authors: Tobias Sehnke1, Matthias Schultalbers2 and Rolf Ernst3 1Control Engineering Excellence Cluster of IAV GmbH, DE; 2Gasoline Engines, IAV GmbH, DE; 3Inst. of Comput. & Network Eng, Tech. Univ. Braunschweig, DE Abstract The functionalities of automotive control are distributed over a large number of independently developed components that are interconnected by complex data dependencies. During integration it is critical to ensure the functional correctness of each component, due to the safety-critical nature of the automotive system. Thus existing integration processes ensure that interfaces are syntactically correct. Still in many cases communicated signals are semantically incompatible. This results in complicated errors that are hard to detect and fix. Moreover, existing component languages do not provide applicable means for the description and control of correspondent requirements. In this paper we present a novel methodology for an automated identification of integration errors in automotive control software. The key aspect of our approach are contracts, which are used to disclose domain level requirements. These contracts are then checked during integration supported by existing tools. A case study involving an existing engine control software shows the applicability of our approach by detecting a significant number of formerly unknown integration errors. Download Paper (PDF; Only available from the DATE venue WiFi)
IP5-5	MODELING AND INTEGRATING PHYSICAL ENVIRONMENT ASSUMPTIONS IN MEDICAL CYBER-PHYSICAL SYSTEM DESIGN Speaker: Chunhui Guo, Illinois Institute of Technology, US Authors: Zhicheng Fu1, Chunhui Guo1, Shangping Ren1, Yu Jiang2 and Lui Sha3 1Illinois Institute of Technology, US; 2Tsinghua University, CN; 3University of Illinois at Urbana-Champaign, US Abstract Implicit physical environment assumptions made by safety critical cyber-physical systems, such as medical cyber- physical systems (M-CPS), can lead to catastrophes. Several recent U.S. Food and Drug Administration (FDA) medical device recalls are due to implicit physical environment assumptions. In this paper, we develop a mathematical assumption model and composition rules that allow M-CPS engineers to explicitly and precisely specify assumptions about the physical environment in which the designed M-CPS operates. Algorithms are developed to integrate the mathematical assumption model with system model so that the safety of the system can be not only validated by both medical and engineering professionals but also formally verified by existing formal verification tools. We use an FDA recalled medical ventilator scenario as a case study to show how the mathematical assumption model and its integration in M-CPS design may improve the safety of the ventilator and M-CPS in general. Download Paper (PDF; Only available from the DATE venue WiFi)
IP5-6	A UTILITY-DRIVEN DATA TRANSMISSION OPTIMIZATION STRATEGY IN LARGE SCALE CYBER-PHYSICAL SYSTEMS Speaker: Bei Yu, The Chinese University of Hong Kong, HK Authors: Soumi Chattopadhyay1, Ansuman Banerjee1 and Bei Yu2 1Indian Statistical Institute, IN; 2The Chinese University of Hong Kong, HK Abstract In this paper, we examine the problem of data dissemination and optimization in the context of a large scale distributed cyber-physical system (CPS), and propose a novel rule-based mechanism for effective observation collection and transmission. Our work rests on the idea that all observations on all parameters are not required at all times, and thereby, selective data transmission can reduce sensor workload significantly. Experiments show the efficacy of our proposal. Download Paper (PDF; Only available from the DATE venue WiFi)
IP5-7	PROTECT NON-VOLATILE MEMORY FROM WEAR-OUT ATTACK BASED ON TIMING DIFFERENCE OF ROW BUFFER HIT/MISS Speaker: Haiyu Mao, Tsinghua University, CN Authors: Haiyu Mao1, Xian Zhang2, Guangyu Sun2 and Jiwu Shu1 1Tsinghua University, CN; 2Peking University, CN Abstract Non-volatile Memories(NVMs), such as PCM and ReRAM, have been widely proposed for future main memory design because of their low standby power, high storage density, fast access speed. However, these NVMs suffer from the write endurance problem. In order to prevent a malicious program from wearing out NVMs deliberately, researchers have proposed various wear-leveling methods, which remap logical addresses to physical addresses randomly and dynamically. However, we discover that side channel leakage based on NVM row buffer hit information can reveal details of address remappings. Consequently, it can be leveraged to side-step the wear-leveling. Our simulation shows that the proposed attack method in this paper can wear out a NVM within 137 seconds, even with the protection of state-of-the-art wear-leveling schemes. To counteract this attack, we further introduce an effective countermeasure named Intra-Row Swap(IRS) to hide the wear-leveling details. The basic idea is to enable an additional intra-row block swap when a new logical address is remapped to the memory row. Experiments demonstrate that IRS can secure NVMs with negligible timing/energy overhead, compared with previous works. Download Paper (PDF; Only available from the DATE venue WiFi)
IP5-8	EFFECTS OF CELL SHAPES ON THE ROUTABILITY OF DIGITAL MICROFLUIDIC BIOCHIPS Speaker: Oliver Keszöcze, University of Bremen, DE Authors: Kevin Leonard Schneider1, Oliver Keszocze1, Jannis Stoppe1 and Rolf Drechsler2 1University of Bremen, DE; 2University of Bremen/DFKI GmbH, DE Abstract Digital microfluidic biochips (DMFBs) are an emerging technology promising a high degree of automation in laboratory procedures by means of manipulating small discretized amounts of fluids. A crucial part in conducting experiments on biochips is the routing of discretized droplets. While doing so, droplets must not enter each others' interference region to avoid unintended mixing. This leads to cells in the proximity of the droplet being impassable for others. For different cell shapes, the effect of these temporary blockages varies as the adjacency of cells changes with their shapes. Yet, no evaluation with respect to routability in relation to cell shapes has been conducted so far. This paper analyses and compares various tessellations for the field of cells. Routing benchmarks are mapped to these and the results are compared in order to determine if and how cell shapes affect the performance of DMFBs, showing that certain cell shapes are superior to others. Download Paper (PDF; Only available from the DATE venue WiFi)
IP5-9	LESS: BIG DATA SKETCHING AND ENCRYPTION ON LOW POWER PLATFORM Speaker: Amey Kulkarni, University of Maryland Baltimore County, US Authors: Amey Kulkarni1, Colin Shea2, Houman Homayoun3 and Tinoosh Mohsenin2 1University of Maryland, Baltimore County, US; 2University of Maryland Baltimore County, US; 3George Mason University, US Abstract Ever-growing IoT demands big data processing and cognitive computing on mobile and battery operated devices. However, big data processing on low power embedded cores is challenging due to their limited communication bandwidth and on-chip storage. Additionally, IoT and cloud-based computing demand low overhead security kernel to avoid data breaches. In this paper, we propose a Light-weight Encryption using Scalable Sketching (LESS) framework for big data sketching and encryption using One-Time Random Linear Projections (OTRLP). OTRLP encoded matrix makes the Known Plaintext Attacks (KPA) ineffective, and attackers cannot gain significant information from plaintext-ciphertext pair. LESS framework can reduce data up to 67\% with 3.81~dB signal-to-reconstruction error rate (SRER). This framework has two important kernels "sketching" and "sketch-reconstruction", the latter is computationally intensive and costly. We propose to accelerate the sketch reconstruction using Orthogonal Matching Pursuit (OMP) on a domain specific many-core hardware named Power Efficient Nano Cluster (PENC) designed by authors. Detailed performance and power analysis suggests that PENC platform has 15x and 200x less energy consumption and 8x and 177x faster reconstruction time as compared to low power ARM CPU, and K1 GPU, respectively. To demonstrate efficiency of LESS framework, we integrate it with Hadoop MapReduce platform for objects and scenes identification application. The full hardware integration consists of tiny ARM cores which perform task scheduling and objects identification application, while PENC acts as an accelerator for sketch reconstruction. The full hardware integration results show that the LESS framework achieves 46% reduction in data transfers with very low execution overhead of 0.11% and negligible energy overhead of 0.001% when tested for 2.6GB streaming input data. The heterogeneous LESS framework requires 2x less transfer time and achieves 2.25x higher throughput per watt compared to MapReduce platform. Download Paper (PDF; Only available from the DATE venue WiFi)
IP5-10	TRUNCAPP: A TRUNCATION-BASED APPROXIMATE DIVIDER FOR ENERGY EFFICIENT DSP APPLICATIONS Speaker: Shaghayegh Vahdat, University of Tehran, IR Authors: Shaghayegh Vahdat1, Mehdi Kamal1, Ali Afzali-Kusha1, Zainalabedin Navabi1 and Massoud Pedram2 1University of Tehran, IR; 2University of Southern California, US Abstract In this paper, we present a high speed yet energy efficient approximate divider where the division operation is performed by multiplying the dividend by the inverse of the divisor. In this structure, truncated value of the dividend is multiplied exactly (approximately) by the approximate inverse value of divisor. To assess the efficacy of the proposed divider, its design parameters are extracted and compared to those of a number of prior art dividers in a 45nm CMOS technology. Results reveal that this structure provides 66% and 52% improvements in the area and energy consumption, respectively, compared to the most advanced prior art approximate divider. In addition, delay and energy consumption of the division operation are reduced about 94.4% and 99.93%, respectively, compared to those of an exact SRT radix-4 divider. Finally, the efficacy of the proposed divider in image processing application is studied. Download Paper (PDF; Only available from the DATE venue WiFi)
IP5-11	TIMING-AWARE WIRE WIDTH OPTIMIZATION FOR SADP PROCESS Speaker: Youngsoo Song, KAIST, KR Authors: Youngsoo Song, Sangmin Kim and Youngsoo Shin, School of Electrical Engineering, KAIST, KR Abstract With the scaling of the minimum feature size, RC delay of interconnect is relatively getting more critical in next node technology. SADP is one of the popular processes used in sub-7nm technology. For SADP process, we can increase wire width using patterns formed by block mask, which can reduce wire resistance of critical nets. We determine the direction and length of each wire widening, so that the resulting layout is conflict-free. We convert this as a maximum weight independent set problem and solve this by formulating an ILP. For various test circuits, the wire resistance of critical nets was reduced on average by 18.5%, which led to 9.9% reduction in clock period. The wire width optimization in SADP process can give an insight into timing optimization through the enhancement of fabrication process. Download Paper (PDF; Only available from the DATE venue WiFi)
IP5-12	FORMAL TIMING ANALYSIS OF NON-SCHEDULED TRAFFIC IN AUTOMOTIVE SCHEDULED TSN NETWORKS Speaker: Jürgen Teich, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE Authors: Fedor Smirnov1, Michael Glaß2, Felix Reimann3 and Jürgen Teich1 1Friedrich-Alexander-Universität Erlangen-Nürnberg, DE; 2Ulm University, DE; 3Audi Electronics Venture GmbH, DE Abstract To cope with requirements for low latency, the upcoming Ethernet standard Time-Sensitive Networking (TSN) provides enhancements for scheduled traffic, enabling mixedcriticality networks where critical messages are sent according to a system-wide schedule. While these networks provide a completely predictable behavior of the scheduled traffic by construction, timing analysis of the critical non-scheduled traffic with hard deadlines remains an unsolved issue. State-of-the-art analysis approaches consider the interference that unscheduled messages impose on each other, but there is currently no approach to determine the worst-case interference that can be imposed by scheduled traffic, the so-called schedule interference (SI), without relying on restrictions of the shape of the schedule. Considering all possible interference scenarios during each calculation of the SI is impractical, as it results in an explosion of the computation time. As a remedy, this paper proposes a) an approach to integrate the analysis of the worst-case SI into state-of-the-art timing analysis approaches and b) preprocessing techniques that reduce the computation time of the SI-calculation by several orders of magnitude without introducing any pessimism. Download Paper (PDF; Only available from the DATE venue WiFi)
IP5-13	ULTRA LOW-POWER VISUAL ODOMETRY FOR NANO-SCALE UNMANNED AERIAL VEHICLES Speaker: Daniele Palossi, ETH Zurich, CH Authors: Daniele Palossi1, Andrea Marongiu2 and Luca Benini3 1ETH - Zurich, CH; 2Swiss Federal Institute of Technology in Zurich (ETHZ), CH; 3Università di Bologna, IT Abstract One of the fundamental functionalities for autonomous navigation of Unmanned Aerial Vehicles (UAVs) is the hovering capability. State-of-the-art techniques for implementing hovering on standard-size UAVs process camera stream to determine position and orientation (visual odometry). Similar techniques are considered unaffordable in the context of nano-scale UAVs (i.e. few centimeters of diameter), where the ultra-constrained power-envelopes of tiny rotor-crafts limit the on-board computational capabilities to those of low-power microcontrollers. In this work we study how the emerging ultra-low-power parallel computing paradigm could enable the execution of complex hovering algorithmic flows onto nano-scale UAVs. We provide insight on the software pipeline, the parallelization opportunities and the impact of several algorithmic enhancements. Results demonstrate that the proposed software flow and architecture can deliver unprecedented GOPS/W, achieving 117 frame-per-second within a power envelope of 10 mW. Download Paper (PDF; Only available from the DATE venue WiFi)
IP5-14	LONG RANGE WIRELESS SENSING POWERED BY PLANT-MICROBIAL FUEL CELL Speaker: Maurizio Rossi, University of Trento, IT Authors: Maurizio Rossi, Pietro Tosato, Luca Gemma, Luca Torquati, Cristian Catania, Sergio Camalò and Davide Brunelli, University of Trento, IT Abstract Going low power and having a low or neutral impact on the environment is key for embedded systems, as pervasive and wearable consumer electronics is growing. In this paper, we present a self-sustaining, ultra-low power device, supplied by a Plant-Microbial Fuel Cell (PMFC) and capable of smart sensing and long-range communication. The use of a PMFC as a power source is challenging but has many advantages like the only requirement of watering the plant. The system uses aggressive power management thanks to FRAM technology exploited to retain microcontroller status and to shutdown electronics without losing context information. Experimental results show that the proposed system paves the way to energy neutral sensors powered by biosystems available almost anywhere on Earth. Download Paper (PDF; Only available from the DATE venue WiFi)
IP5-15	ON THE COOPERATIVE AUTOMATIC LANE CHANGE: SPEED SYNCHRONIZATION AND AUTOMATIC "COURTESY" Speaker: Alexandre Lombard, UTBM, FR Authors: Alexandre Lombard1, Florent Perronet1, Abdeljalil Abbas-Turki2 and Abdellah El-Moudni1 1UTBM, FR; 2Université de Technologie de Belfort-Montbéliard, FR Abstract The recent ability of some vehicles to handle autonomously the lane change maneuvers, and the progressive equipment of roads and vehicles with ITS-G5 units motivate this paper to consider the case of road narrowing that requires a lane change because one lane is occupied by road works for maintenance, incidents and so on. This paper extends the approaches of cooperative speed synchronization at intersections. Because of the complexity of the overall system, it considers each automatic lane change as a mobile (unfixed) intersection in which vehicles synchronize their velocities. The wireless communication allows each vehicle to increase its field of view to negotiate its merging with the other equipped vehicles. Hence, the proposed approach introduces a kind of automatic "courtesy" between equipped vehicles. The paper defines the intersection point between each pair of vehicles and the suited protocol to safely reach the new lane. The protocol can be handled by the new work item (NWI) that has been created at ETSI to realize platooning and cooperative adaptive cruise control. Besides enhancing safety, the simulation results show that the main advantage of the approach is the energy saving by smoothing the traffic. Download Paper (PDF; Only available from the DATE venue WiFi)
IP5-16	EVALUATING MATRIX REPRESENTATIONS FOR ERROR-TOLERANT COMPUTING Speaker: Pareesa Golnari, Princeton University, US Authors: Pareesa Ameneh Golnari and Sharad Malik, Princeton University, US Abstract We propose a methodology to determine the suitability of different data representations in terms of their error-tolerance for a given application with accelerator-based computing. This methodology helps match the characteristics of a representation to the data access patterns in an application. For this, we first identify a benchmark of key kernels from linear algebra that can be used to construct applications of interest using any of several widely used data representations. This is then used in an experimental framework for studying the error tolerance of a specific data format for an application. As case studies, we evaluate the error-tolerance of seven data-formats on sparse matrix to vector multiplication, diagonal add, and two machine learning applications i) principal component analysis (PCA), which is a statistical technique widely used in data analysis and ii) movie recommendation system with Restricted Boltzmann Machine (RBM) as the core. We observe that the Dense format behaves well for complicated data accesses such as diagonal accessing but is poor in utilizing local memory. Sparse formats with simpler addressing methods and a careful selection of stored information, e.g., CRS and ELLPACK, demonstrate a better error-tolerance for most of our target applications. Download Paper (PDF; Only available from the DATE venue WiFi)
IP5-17	SIMULATION-BASED DESIGN PROCEDURE FOR SUB 1 V CMOS CURRENT REFERENCE Speaker: Dmitry Osipov, University of Bremen, DE Authors: Dmitry Osipov and Steffen Paul, University of Bremen, DE Abstract This paper presents a new compact current reference and a simulation-based design procedure to establish the circuit parameters quicly and efficiently. To verify the proposed design procedure, two sub 1~V example circuits for two different reference current values (80 nA and 800 nA) were designed and simulated using 0.35 µm CMOS technology. The circuits are robust against supply voltage variation without the need for external bandgap. A line sensitivity of approximately 1-2%/V over the supply voltage range from sub 1 V is achieved in both cases. The simulated temperature coefficient (TC) values are 93 ppm/°C and 197 ppm/°C in the temperature range from 0°C to 120°C for the 800 nA and 80 nA references, respectively. Download Paper (PDF; Only available from the DATE venue WiFi)