5.6 Reuse and Integration of Test, Debug, and Reliability Infrastructure

Time	Label	Presentation Title Authors
08:30	5.6.1	FAULT CLUSTERING TECHNIQUE FOR 3D MEMORY BISR Speaker: Tianjian Li, Shanghai Jiao Tong University, CN Authors: Tianjian Li¹, Yan Han¹, Xiaoyao Liang¹, Hsien-Hsin S. Lee² and Li Jiang³ ¹Shanghai Jiao Tong University, CN; ²TSMC / Georgia Tech, TW; ³Department of Computer Science and Engineering, Shanghai Jiao Tong University, CN Abstract Three Dimensional (3D) memory has gained a great momentum because of its large storage capacity, bandwidth and etc. A critical challenge for 3D memory is the significant yield loss due to the disruptive integration process: any memory die that cannot be successfully repaired leads to the failure of the whole stack. The repair ratio of each die must be as high as possible to guarantee the overall yield. Existing memory repair methods, however, follow the traditional way of using redundancies: a redundant row/column replaces a row/column containing few or even one faulty cell. We propose a novel technique specifically in 3D memory that can overcome this limitation. It can cluster faulty cells across layers to the same row/column in the same memory array so that each redundant row/column can repair more "faults". Moreover, it can be applied to the existing repair algorithms. We design the BIST and BISR modules to implement the proposed repair technique. Experimental results show more than 71% enhancement of the repair ratio over the global 3D GESP solution and 80% redundancy-cost reduction, respectively. Download Paper (PDF; Only available from the DATE venue WiFi)
09:00	5.6.2	ARCHITECTURAL EVALUATIONS ON TSV REDUNDANCY FOR RELIABILITY ENHANCEMENT Speaker: Yen-Hao Chen, National Tsing Hua University, Taiwan, TW Authors: YenHao Chen¹, Chien-Pang Chiu¹, Russell Barnes² and TingTing Hwang¹ ¹National Tsing Hua University, R.O.C, TW; ²University of California at Santa Barbara, US Abstract Three-dimensional Integrated Circuits (3D-ICs) is a next-generation technology that could be a solution to overcome the scaling problem. It stacks dies with Through-Silicon Vias (TSVs) so that signals can be transmitted through dies vertically. However, researchers have noticed that the aging effect due to the electormigration (EM) may result in faulty TSVs and affect the chip lifetime [1]. Several redundant TSV architectures have been proposed to address this issue. By replacing the faulty TSV with redundant TSVs which are added at design time, chips can achieve better reliability and longer lifetime. In this paper, we will study the tradeoff of various redundant TSV architectures in terms of effectiveness and cost. To allow the measurement of reliability more realistically, we propose a new standard, repair rate, to appraise the redundant TSV architectures. Moreover, to design a more flexible and efficient structure, we enhance the ring-based design [2] that can adjust the size of the TSV block and TSV redundancy. Download Paper (PDF; Only available from the DATE venue WiFi)
09:30	5.6.3	REUSING TRACE BUFFERS TO ENHANCE CACHE PERFORMANCE Speaker: Neetu Jindal, PhD, IN Authors: Neetu Jindal, Preeti Ranjan Panda and Smruti R. Sarangi, Indian Institute of Technology Delhi, IN Abstract With the increasing complexity of modern Systems-on-Chip, the possibility of functional errors escaping design verification is growing. Post-silicon validation targets the discovery of these errors in early hardware prototypes. Due to limited visibility and observability, dedicated design-for-debug (DFD) hardware such as trace buffers are inserted to aid post-silicon validation. In spite of its benefit, such hardware incurs area overheads, which impose size limitations. However, the overhead could be overcome if the area dedicated to DFD could be reused in-field. In this work, we present a novel method for reusing an existing trace buffer as a victim cache of a processor to enhance performance. The trace buffer storage space is reused for the victim cache, with a small additional controller logic. Experimental results on several benchmarks and trace buffer sizes show that the proposed approach can enhance the average performance by up to 8.3% over a baseline architecture. We also propose a strategy for dynamic power management of the structure, to enable saving energy with negligible impact on performance. Download Paper (PDF; Only available from the DATE venue WiFi)
09:45	5.6.4	OPTIMIZATION OF RETARGETING FOR IEEE 1149.1 TAP CONTROLLERS WITH EMBEDDED COMPRESSION Speaker: Sebastian Huhn, University of Bremen, DE Authors: Sebastian Huhn¹, Stephan Eggersglüß¹, Krishnendu Chakrabarty² and Rolf Drechsler³ ¹University of Bremen, DE; ²Duke University, US; ³University of Bremen/DFKI GmbH, DE Abstract We present a formal optimization technique that enables retargeting for codeword-based IEEE 1149.1-compliant TAP controllers. The proposed method addresses the problem of high test data volume and Test Application Time (TAT) for a system-on-chip design during board or in-field testing, as well as during debugging. This procedure determines an optimal set of codewords with respect to given hardware constraints, e.g., embedded dictionary size and the interface to the Test Data Register in the IEEE 1149.1 Std. A complete traversal of the spanned search space is possible through the use of formal methods. An optimal set of codewords can be determined, which is directly utilized for retargeting. The proposed method is evaluated using test data with high-entropy, which is known to be the least amenable to compression, as well as input data for debugging and Functional Verification (FV) test data. Our results show a compression ratio improvement of more than 30% and a reduction in TAT up to 20% compared to previous techniques. Download Paper (PDF; Only available from the DATE venue WiFi)
10:00	IP2-17, 700	NOVEL MAGNETIC BURN-IN FOR RETENTION TESTING OF STTRAM Speaker: Swaroop Ghosh, Pennsylvania State University, US Authors: Mohammad Nasim Imtiaz Khan, Anirudh Iyengar and Swaroop Ghosh, Pennsylvania State University, US Abstract Spin-Transfer Torque RAM (STTRAM) is an emerging Non-Volatile Memory (NVM) technology that has drawn significant attention due to complete elimination of bitcell leakage. However, it brings new challenges in characteriz-ing the retention time of the array during test. Significant shift of retention time under static (process variation (PV)) and dynamic (voltage, temperature fluctuation) variability furthers this issue. In this paper, we propose a novel mag-netic burn-in (MBI) test which can be implemented with minimal changes in the existing test flow to enable STTRAM retention testing at short test time. The magnetic burn-in is also combined with thermal burn-in (MBI+BI) for further compression of retention and test time. Simula-tion results indicate MBI with 220Oe (at 25C) can improve the test time by 3.71x1013 X while MBI+BI with 220Oe at 125C can improve the test time by 1.97x1014X. Download Paper (PDF; Only available from the DATE venue WiFi)
10:00		End of session Coffee Break in Exhibition Area On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area. Tuesday, March 28, 2017 Coffee Break 10:30 - 11:30 Coffee Break 16:00 - 17:00 Wednesday, March 29, 2017 Coffee Break 10:00 - 11:00 Coffee Break 16:00 - 17:00 Thursday, March 30, 2017 Coffee Break 10:00 - 11:00 Coffee Break 15:30 - 16:00

Time

Label

Presentation Title
Authors

08:30

5.6.1

FAULT CLUSTERING TECHNIQUE FOR 3D MEMORY BISR
Speaker:
Tianjian Li, Shanghai Jiao Tong University, CN
Authors:
Tianjian Li¹, Yan Han¹, Xiaoyao Liang¹, Hsien-Hsin S. Lee² and Li Jiang³
¹Shanghai Jiao Tong University, CN; ²TSMC / Georgia Tech, TW; ³Department of Computer Science and Engineering, Shanghai Jiao Tong University, CN
Abstract
Three Dimensional (3D) memory has gained a great momentum because of its large storage capacity, bandwidth and etc. A critical challenge for 3D memory is the significant yield loss due to the disruptive integration process: any memory die that cannot be successfully repaired leads to the failure of the whole stack. The repair ratio of each die must be as high as possible to guarantee the overall yield. Existing memory repair methods, however, follow the traditional way of using redundancies: a redundant row/column replaces a row/column containing few or even one faulty cell. We propose a novel technique specifically in 3D memory that can overcome this limitation. It can cluster faulty cells across layers to the same row/column in the same memory array so that each redundant row/column can repair more "faults". Moreover, it can be applied to the existing repair algorithms. We design the BIST and BISR modules to implement the proposed repair technique. Experimental results show more than 71% enhancement of the repair ratio over the global 3D GESP solution and 80% redundancy-cost reduction, respectively.
Download Paper (PDF; Only available from the DATE venue WiFi)

09:00

5.6.2

ARCHITECTURAL EVALUATIONS ON TSV REDUNDANCY FOR RELIABILITY ENHANCEMENT
Speaker:
Yen-Hao Chen, National Tsing Hua University, Taiwan, TW
Authors:
YenHao Chen¹, Chien-Pang Chiu¹, Russell Barnes² and TingTing Hwang¹
¹National Tsing Hua University, R.O.C, TW; ²University of California at Santa Barbara, US
Abstract
Three-dimensional Integrated Circuits (3D-ICs) is a next-generation technology that could be a solution to overcome the scaling problem. It stacks dies with Through-Silicon Vias (TSVs) so that signals can be transmitted through dies vertically. However, researchers have noticed that the aging effect due to the electormigration (EM) may result in faulty TSVs and affect the chip lifetime [1]. Several redundant TSV architectures have been proposed to address this issue. By replacing the faulty TSV with redundant TSVs which are added at design time, chips can achieve better reliability and longer lifetime. In this paper, we will study the tradeoff of various redundant TSV architectures in terms of effectiveness and cost. To allow the measurement of reliability more realistically, we propose a new standard, repair rate, to appraise the redundant TSV architectures. Moreover, to design a more flexible and efficient structure, we enhance the ring-based design [2] that can adjust the size of the TSV block and TSV redundancy.
Download Paper (PDF; Only available from the DATE venue WiFi)

09:30

5.6.3

REUSING TRACE BUFFERS TO ENHANCE CACHE PERFORMANCE
Speaker:
Neetu Jindal, PhD, IN
Authors:
Neetu Jindal, Preeti Ranjan Panda and Smruti R. Sarangi, Indian Institute of Technology Delhi, IN
Abstract
With the increasing complexity of modern Systems-on-Chip, the possibility of functional errors escaping design verification is growing. Post-silicon validation targets the discovery of these errors in early hardware prototypes. Due to limited visibility and observability, dedicated design-for-debug (DFD) hardware such as trace buffers are inserted to aid post-silicon validation. In spite of its benefit, such hardware incurs area overheads, which impose size limitations. However, the overhead could be overcome if the area dedicated to DFD could be reused in-field. In this work, we present a novel method for reusing an existing trace buffer as a victim cache of a processor to enhance performance. The trace buffer storage space is reused for the victim cache, with a small additional controller logic. Experimental results on several benchmarks and trace buffer sizes show that the proposed approach can enhance the average performance by up to 8.3% over a baseline architecture. We also propose a strategy for dynamic power management of the structure, to enable saving energy with negligible impact on performance.
Download Paper (PDF; Only available from the DATE venue WiFi)

09:45

5.6.4

OPTIMIZATION OF RETARGETING FOR IEEE 1149.1 TAP CONTROLLERS WITH EMBEDDED COMPRESSION
Speaker:
Sebastian Huhn, University of Bremen, DE
Authors:
Sebastian Huhn¹, Stephan Eggersglüß¹, Krishnendu Chakrabarty² and Rolf Drechsler³
¹University of Bremen, DE; ²Duke University, US; ³University of Bremen/DFKI GmbH, DE
Abstract
We present a formal optimization technique that enables retargeting for codeword-based IEEE 1149.1-compliant TAP controllers. The proposed method addresses the problem of high test data volume and Test Application Time (TAT) for a system-on-chip design during board or in-field testing, as well as during debugging. This procedure determines an optimal set of codewords with respect to given hardware constraints, e.g., embedded dictionary size and the interface to the Test Data Register in the IEEE 1149.1 Std. A complete traversal of the spanned search space is possible through the use of formal methods. An optimal set of codewords can be determined, which is directly utilized for retargeting. The proposed method is evaluated using test data with high-entropy, which is known to be the least amenable to compression, as well as input data for debugging and Functional Verification (FV) test data. Our results show a compression ratio improvement of more than 30% and a reduction in TAT up to 20% compared to previous techniques.
Download Paper (PDF; Only available from the DATE venue WiFi)

10:00

IP2-17, 700

NOVEL MAGNETIC BURN-IN FOR RETENTION TESTING OF STTRAM
Speaker:
Swaroop Ghosh, Pennsylvania State University, US
Authors:
Mohammad Nasim Imtiaz Khan, Anirudh Iyengar and Swaroop Ghosh, Pennsylvania State University, US
Abstract
Spin-Transfer Torque RAM (STTRAM) is an emerging Non-Volatile Memory (NVM) technology that has drawn significant attention due to complete elimination of bitcell leakage. However, it brings new challenges in characteriz-ing the retention time of the array during test. Significant shift of retention time under static (process variation (PV)) and dynamic (voltage, temperature fluctuation) variability furthers this issue. In this paper, we propose a novel mag-netic burn-in (MBI) test which can be implemented with minimal changes in the existing test flow to enable STTRAM retention testing at short test time. The magnetic burn-in is also combined with thermal burn-in (MBI+BI) for further compression of retention and test time. Simula-tion results indicate MBI with 220Oe (at 25C) can improve the test time by 3.71x1013 X while MBI+BI with 220Oe at 125C can improve the test time by 1.97x1014X.
Download Paper (PDF; Only available from the DATE venue WiFi)

10:00

End of session
Coffee Break in Exhibition Area

On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area.

Tuesday, March 28, 2017