5.5 Hot Topic Session: Spintronics-based Computing

Time	Label	Presentation Title Authors
08:30	5.5.1	MAGNETIC TUNNEL JUNCTION ENABLED ALL-SPIN STOCHASTIC SPIKING NEURAL NETWORK Speaker: Kaushik Roy, Purdue University, US Authors: Gopalakrishnan Srinivasan, Abhronil Sengupta and Kaushik Roy, Purdue University, US Abstract Biologically-inspired spiking neural networks (SNNs) have attracted significant research interest due to their inherent computational efficiency in performing classification and recognition tasks. The conventional CMOS-based implementations of large-scale SNNs are power intensive. This is a consequence of the fundamental mismatch between the technology used to realize the neurons and synapses, and the neuroscience mechanisms governing their operation, leading to area-expensive circuit designs. In this work, we present a three- terminal spintronic device, namely, the magnetic tunnel junction (MTJ)-heavy metal (HM) heterostructure that is inherently capable of emulating the neuronal and synaptic dynamics. We exploit the stochastic switching behavior of the MTJ in the presence of thermal noise to mimic the probabilistic spiking of cortical neurons, and the conditional change in the state of a binary synapse based on the pre- and post-synaptic spiking activity required for plasticity. We demonstrate the efficacy of a crossbar organization of our MTJ-HM based stochastic SNN in digit recognition using a comprehensive device-circuit-system simulation framework. The energy efficiency of the proposed system stems from the ultra-low switching energy of the MTJ-HM device, and the in-memory computation rendered possible by the localized arrangement of the computational units (neurons) and non-volatile synaptic memory in such crossbar architectures. Download Paper (PDF; Only available from the DATE venue WiFi)
08:48	5.5.2	EMBEDDED SYSTEMS TO HIGH PERFORMANCE COMPUTING USING STT-MRAM Speaker: Sophiane Senni, LIRMM, FR Authors: Sophiane SENNI¹, Thibaud Delobelle¹, Odilia Coi¹, Pierre-Yves Péneau², Lionel Torres³, Abdoulaye Gamatie⁴, Pascal Benoit³ and Gilles Sassatelli⁵ ¹LIRMM, FR; ²LIRMM - CNRS, FR; ³University of Montpellier, FR; ⁴CNRS LIRMM / University of Montpellier, FR; ⁵LIRMM CNRS / University of Montpellier 2, FR Abstract The scaling limits of CMOS have pushed many researchers to explore alternative technologies for beyond CMOS circuits. In addition to the increased device variability and process complexity led by the continuous decreasing size of CMOS transistors, heat dissipation effects limit the density and speed of current systems-on-chip. For beyond CMOS systems, the emerging memory technology STT-MRAM is seen as a promising alternative solution. This paper shows first how STTMRAM can improve energy efficiency and reliability of future embedded systems. Then, a hybrid design exploration framework is presented to investigate the potential of STT-MRAM for high performance computing. Download Paper (PDF; Only available from the DATE venue WiFi)
09:06	5.5.3	VOLTAGE-CONTROLLED MRAM FOR WORKING MEMORY: PERSPECTIVES AND CHALLENGE Speaker: Wang Kang, Beihang University, CN Authors: Wang Kang, Liang Chang, Youguang Zhang and Weisheng Zhao, Beihang University, CN Abstract Magnetic random access memory (MRAM) has been widely studied for future nonvolatile working memory candidate. However, the mainstream current (spin transfer torque, STT or spin Hall effect, SHE) driven MRAMs (STT-MRAM or SHE-MRAM) face intrinsic problems in terms of high write power and long latency, significantly limiting the applications for low-power and high-speed working memories. The recently-developed new-generation MRAM, named VCMA-MRAM, which exploits the voltage-controlled magnetic anisotropy (VCMA) effect to write (or assist to write) data information into magnetic tunnel junctions (MTJs), holds the promise to efficiently overcome these problems. Despite the impressive possibility of improving write power and speed, this technology, however, is currently under intensive research and development (R&D), and some challenges still await answers. In this paper, we investigate the perspectives and challenges of VCMA-MRAM for working memories from a cross-layer (device/circuit/architecture) design point of view. We demonstrate that VCMA-MRAM outperforms STT-MRAM and SHE-MRAM in terms of area, speed, energy consumption and instruction-per-cycle (IPC) performance, benefiting from the low-power and high-speed VCMA-driven data writing mechanism. On the other hand, challenges in terms of device fabrication and circuit design should be efficiently addressed before practical applications. Download Paper (PDF; Only available from the DATE venue WiFi)
09:24	5.5.4	THREE-TERMINAL MTJ-BASED NONVOLATILE LOGIC CIRCUITS WITH SELF-TERMINATED WRITING MECHANISM FOR ULTRA-LOW-POWER VLSI PROCESSOR Speaker: Takahiro Hanyu, RIEC, Tohoku University, JP Authors: Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa and Masanori Natsui, Tohoku University, JP Abstract Magnetic-Tunnel Junction (MTJ)-based non-volatile logic circuits have some possibility to solve the power-dissipation problem seriously focusing on the present CMOS-only-based VLSI processors. Three terminal MTJ devices are the promising candidate as nonvolatile storage device to realize such a nonvolatile logic circuit. However, its writing energy is still serious in comparison with conventional CMOS-only-based logic circuits. In this paper, a new MTJ-based nonvolatile logic circuit with self-terminated mechanism is proposed and its energy efficiency is evaluated in comparison with the corresponding previous work. In addition, some recent research topics related to MTJ-based nonvolatile logic-circuit design and its application, such as a computer-aided-design (CAD) tool considering a stochastic MTJ-switching behavior and the application to a resilient "die-hard" VLSI processor against sudden power-supply outage, are also demonstrated. Download Paper (PDF; Only available from the DATE venue WiFi)
09:42	5.5.5	OPPORTUNISTIC WRITE FOR FAST AND RELIABLE STT-MRAM Speaker: Mehdi Tahoori, Karlsruhe Institute of Technology, DE Authors: Nour Sayed¹, Mojtaba Ebrahimi¹, Rajendra Bishnoi² and Mehdi Tahoori¹ ¹Karlsruhe Institute of Technology, DE; ²Karlsruhe Institiute of Technology, DE Abstract Due to the stochastic switching behavior of the bitcell in Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM), an excessive write margin is required to guarantee an acceptable level of reliability and yield. This prevents the usage of STT-MRAM in fast memories such as L1 or L2 caches. The excessive write margin of STT-MRAM can be reduced to a large extent by an opportunistic write (i.e., terminating the write process before all bit switchings are completed) and by reducing thermal stability factor. The bits with unfinished writes have to be processed by robust Error Correction Codes (ECCs). However, such coding schemes have relatively large decoding latencies, which increases the overall read latency significantly. Moreover, thermally induced retention failures can limit the applicability of such schemes. In this paper, we exploit the fact that error detection is much faster than correction. Therefore, the errors can be detected quickly and all erroneous data can be reverted before they arrive critical parts of the system (e.g., commit stage or memory ports). We also provide an adaptive approach to manage temperature-dependent retention failures at runtime. Hence, our proposed approach enables the use of STT-MRAM technology for fast cache applications. Download Paper (PDF; Only available from the DATE venue WiFi)
10:00		End of session Coffee Break in Exhibition Area On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area. Tuesday, March 28, 2017 Coffee Break 10:30 - 11:30 Coffee Break 16:00 - 17:00 Wednesday, March 29, 2017 Coffee Break 10:00 - 11:00 Coffee Break 16:00 - 17:00 Thursday, March 30, 2017 Coffee Break 10:00 - 11:00 Coffee Break 15:30 - 16:00

Time

Label

Presentation Title
Authors

08:30

5.5.1

MAGNETIC TUNNEL JUNCTION ENABLED ALL-SPIN STOCHASTIC SPIKING NEURAL NETWORK
Speaker:
Kaushik Roy, Purdue University, US
Authors:
Gopalakrishnan Srinivasan, Abhronil Sengupta and Kaushik Roy, Purdue University, US
Abstract
Biologically-inspired spiking neural networks (SNNs) have attracted significant research interest due to their inherent computational efficiency in performing classification and recognition tasks. The conventional CMOS-based implementations of large-scale SNNs are power intensive. This is a consequence of the fundamental mismatch between the technology used to realize the neurons and synapses, and the neuroscience mechanisms governing their operation, leading to area-expensive circuit designs. In this work, we present a three- terminal spintronic device, namely, the magnetic tunnel junction (MTJ)-heavy metal (HM) heterostructure that is inherently capable of emulating the neuronal and synaptic dynamics. We exploit the stochastic switching behavior of the MTJ in the presence of thermal noise to mimic the probabilistic spiking of cortical neurons, and the conditional change in the state of a binary synapse based on the pre- and post-synaptic spiking activity required for plasticity. We demonstrate the efficacy of a crossbar organization of our MTJ-HM based stochastic SNN in digit recognition using a comprehensive device-circuit-system simulation framework. The energy efficiency of the proposed system stems from the ultra-low switching energy of the MTJ-HM device, and the in-memory computation rendered possible by the localized arrangement of the computational units (neurons) and non-volatile synaptic memory in such crossbar architectures.
Download Paper (PDF; Only available from the DATE venue WiFi)

08:48

5.5.2

EMBEDDED SYSTEMS TO HIGH PERFORMANCE COMPUTING USING STT-MRAM
Speaker:
Sophiane Senni, LIRMM, FR
Authors:
Sophiane SENNI¹, Thibaud Delobelle¹, Odilia Coi¹, Pierre-Yves Péneau², Lionel Torres³, Abdoulaye Gamatie⁴, Pascal Benoit³ and Gilles Sassatelli⁵
¹LIRMM, FR; ²LIRMM - CNRS, FR; ³University of Montpellier, FR; ⁴CNRS LIRMM / University of Montpellier, FR; ⁵LIRMM CNRS / University of Montpellier 2, FR
Abstract
The scaling limits of CMOS have pushed many researchers to explore alternative technologies for beyond CMOS circuits. In addition to the increased device variability and process complexity led by the continuous decreasing size of CMOS transistors, heat dissipation effects limit the density and speed of current systems-on-chip. For beyond CMOS systems, the emerging memory technology STT-MRAM is seen as a promising alternative solution. This paper shows first how STTMRAM can improve energy efficiency and reliability of future embedded systems. Then, a hybrid design exploration framework is presented to investigate the potential of STT-MRAM for high performance computing.
Download Paper (PDF; Only available from the DATE venue WiFi)

09:06

5.5.3

VOLTAGE-CONTROLLED MRAM FOR WORKING MEMORY: PERSPECTIVES AND CHALLENGE
Speaker:
Wang Kang, Beihang University, CN
Authors:
Wang Kang, Liang Chang, Youguang Zhang and Weisheng Zhao, Beihang University, CN
Abstract
Magnetic random access memory (MRAM) has been widely studied for future nonvolatile working memory candidate. However, the mainstream current (spin transfer torque, STT or spin Hall effect, SHE) driven MRAMs (STT-MRAM or SHE-MRAM) face intrinsic problems in terms of high write power and long latency, significantly limiting the applications for low-power and high-speed working memories. The recently-developed new-generation MRAM, named VCMA-MRAM, which exploits the voltage-controlled magnetic anisotropy (VCMA) effect to write (or assist to write) data information into magnetic tunnel junctions (MTJs), holds the promise to efficiently overcome these problems. Despite the impressive possibility of improving write power and speed, this technology, however, is currently under intensive research and development (R&D), and some challenges still await answers. In this paper, we investigate the perspectives and challenges of VCMA-MRAM for working memories from a cross-layer (device/circuit/architecture) design point of view. We demonstrate that VCMA-MRAM outperforms STT-MRAM and SHE-MRAM in terms of area, speed, energy consumption and instruction-per-cycle (IPC) performance, benefiting from the low-power and high-speed VCMA-driven data writing mechanism. On the other hand, challenges in terms of device fabrication and circuit design should be efficiently addressed before practical applications.
Download Paper (PDF; Only available from the DATE venue WiFi)

09:24

5.5.4

THREE-TERMINAL MTJ-BASED NONVOLATILE LOGIC CIRCUITS WITH SELF-TERMINATED WRITING MECHANISM FOR ULTRA-LOW-POWER VLSI PROCESSOR
Speaker:
Takahiro Hanyu, RIEC, Tohoku University, JP
Authors:
Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa and Masanori Natsui, Tohoku University, JP
Abstract
Magnetic-Tunnel Junction (MTJ)-based non-volatile logic circuits have some possibility to solve the power-dissipation problem seriously focusing on the present CMOS-only-based VLSI processors. Three terminal MTJ devices are the promising candidate as nonvolatile storage device to realize such a nonvolatile logic circuit. However, its writing energy is still serious in comparison with conventional CMOS-only-based logic circuits. In this paper, a new MTJ-based nonvolatile logic circuit with self-terminated mechanism is proposed and its energy efficiency is evaluated in comparison with the corresponding previous work. In addition, some recent research topics related to MTJ-based nonvolatile logic-circuit design and its application, such as a computer-aided-design (CAD) tool considering a stochastic MTJ-switching behavior and the application to a resilient "die-hard" VLSI processor against sudden power-supply outage, are also demonstrated.
Download Paper (PDF; Only available from the DATE venue WiFi)

09:42

5.5.5

OPPORTUNISTIC WRITE FOR FAST AND RELIABLE STT-MRAM
Speaker:
Mehdi Tahoori, Karlsruhe Institute of Technology, DE
Authors:
Nour Sayed¹, Mojtaba Ebrahimi¹, Rajendra Bishnoi² and Mehdi Tahoori¹
¹Karlsruhe Institute of Technology, DE; ²Karlsruhe Institiute of Technology, DE
Abstract
Due to the stochastic switching behavior of the bitcell in Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM), an excessive write margin is required to guarantee an acceptable level of reliability and yield. This prevents the usage of STT-MRAM in fast memories such as L1 or L2 caches. The excessive write margin of STT-MRAM can be reduced to a large extent by an opportunistic write (i.e., terminating the write process before all bit switchings are completed) and by reducing thermal stability factor. The bits with unfinished writes have to be processed by robust Error Correction Codes (ECCs). However, such coding schemes have relatively large decoding latencies, which increases the overall read latency significantly. Moreover, thermally induced retention failures can limit the applicability of such schemes. In this paper, we exploit the fact that error detection is much faster than correction. Therefore, the errors can be detected quickly and all erroneous data can be reverted before they arrive critical parts of the system (e.g., commit stage or memory ports). We also provide an adaptive approach to manage temperature-dependent retention failures at runtime. Hence, our proposed approach enables the use of STT-MRAM technology for fast cache applications.
Download Paper (PDF; Only available from the DATE venue WiFi)

10:00

End of session
Coffee Break in Exhibition Area

On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area.

Tuesday, March 28, 2017