10.5 Emerging NoC Directions

Time	Label	Presentation Title Authors
11:00	10.5.1	MACHINE LEARNING ENABLED POWER-AWARE NETWORK-ON-CHIP DESIGN Speaker: Avinash Kodi, Ohio University, US Authors: Dominic DiTomaso¹, Ashif Sikder¹, Avinash Kodi¹ and Ahmed Louri² ¹Ohio University, US; ²George Washington University, US Abstract Although Network-on-Chips (NoCs) are fast becoming pervasive as the interconnect fabric for multicore architectures and systems-on-chips, they still suffer from excessive static and dynamic power consumption. High dynamic power consumption results from switching and storing data within routers/links while excess static power is consumed when routers and links are not utilized for communication and yet have to be powered up. In this paper, we propose LESSON (Learning Enabled Sleepy Storage Links and Routers in NoCs) to reduce both static and dynamic power consumption by power-gating the links and routers at low network utilization and moving the data storage from within the routers to the links at high network utilization. As the network utilization increases from low-to-high, to accommodate more traffic, we design the same channels to flow traffic in either direction, thereby avoiding complex routing or look-ahead wake-up algorithms. Machine learning algorithms predict when to power-gate the channels and routers and when to increase the channel bandwidths such that power savings are maximized while performance penalty is minimized. Our results show that we can improve total network power consumption when compared to conventional NoC buffer designs by 85.6% and when compared with aggressive NoC buffer designs by 31.7%. Our predictor shows marginal performance penalties and by dynamically changing the direction of the links, we can improve packet latency by 14%. Download Paper (PDF; Only available from the DATE venue WiFi)
11:30	10.5.2	PERFORMANCE EVALUATION AND DESIGN TRADE-OFFS FOR WIRELESS-ENABLED SMART NOC Speaker: Karthi Duraisamy, Washington State University, US Authors: Karthi Duraisamy and Partha Pande, Washington State University, US Abstract SMART (Single-Cycle Multi-hop Asynchronous Repeated Traversal) NoC architectures enable single cycle data transfers, even between the physically far apart nodes. However, enabling single cycle hops over long distance restricts the achievable clock frequency of the system. In other words, increasing the NoC clock frequency lowers the number of hops that can be traversed in a single-cycle in a conventional SMART NoC. In this work, we demonstrate that by integrating wireless links and a novel look-ahead request mechanism in the SMART NoC, it is possible to enable low-latency and energy efficient data transfers, even when the system is designed with high clock frequencies. For various applications considered in this work, our wireless-enabled SMART (WiSMART) NoC achieves on an average 33% reduction in message latency compared to the wireline SMART mesh NoC. This network level improvement translates into 16% savings in full system energy-delay-product. Download Paper (PDF; Only available from the DATE venue WiFi)
12:00	10.5.3	ROBUST TSV-BASED 3D NOC DESIGN TO COUNTERACT ELECTROMIGRATION AND CROSSTALK NOISE Speaker: Partha Pande, Washington State University, US Authors: Sourav Das¹, Janardhan Rao Doppa¹, Partha Pande¹ and Krishnendu Chakrabarty² ¹Washington State University, US; ²Duke University, US Abstract A 3D network-on-chip (3D NoC) is an enabler for the design of high-performance and energy-efficient manycore chips. Most popular 3D NoCs utilize the Through-Silicon-Via (TSV)-based vertical links (VLs) as the communication pillars between the planar dies. However, the TSVs in a 3D NoC may fail due to both workload-induced stress and crosstalk capacitance. This failure negatively affects the overall achievable performance of the 3D NoC. In this work, we analyze the joint effects of workload-induced stress and crosstalk on the TSV mean-time-to-failure (MTTF) and hence the 3D NoC lifetime. We demonstrate that if we only consider the effects of electromigration on the TSVs due to workload-induced stress then the estimated MTTF and the subsequently lifetime of 3D NoC are too optimistic. Due to the combined effects of workload and crosstalk noise, the lifetime of 3D NoC reduces significantly. Subsequently, we demonstrate that a spare TSV allocation methodology considering the joint effects of workload and crosstalk noise enhances the lifetime of the 3D NoC by a factor of 4.6 compared to when only the workload is considered for a given spare budget of 5%. Download Paper (PDF; Only available from the DATE venue WiFi)
12:15	10.5.4	PERFORMANCE AND ENERGY AWARE WAVELENGTH ALLOCATION ON RING-BASED WDM 3D OPTICAL NOC Speaker: Jiating Luo, INRIA/IRISA, FR Authors: Jiating Luo¹, Ashraf Elantably¹, Pham Van-Dung¹, Cedric Killian¹, Daniel Chillet¹, Sébastien Le Beux², Olivier Sentieys³ and Ian O'Connor² ¹INRIA/IRISA, FR; ²Lyon Institute of Nanotechnology, FR; ³INRIA, FR Abstract Optical Network-on-Chip (ONoC) is a promising communication medium for large-scale Multiprocessor System on Chip (MPSoC). ONoC outperforms classical electrical NoC in terms of throughput and latency. The medium can support multiple transactions at the same time on different wavelengths by using Wavelength Division Multiplexing (WDM). Moreover multiple wavelengths can be used as high-bandwidth channel to reduce transmission time. However, multiple signals sharing simultaneously a waveguide can lead to inter-channel crosstalk noise. This problem impacts the Signal to Noise Ratio (SNR) of the optical signal, which leads to an increase in the Bit Error Rate (BER) at the receiver side. In this paper we first formulate the crosstalk noise and execution time models and then propose a Wavelength Allocation (WA) method in a ring-based WDM ONoC allowing to search for performance and energy trade-offs, based on the application constraints. As result, most promising WA solutions are highlighted for a defined application mapping onto 16-core WDM ONoC. Download Paper (PDF; Only available from the DATE venue WiFi)
12:30		End of session Lunch Break in Garden Foyer Keynote Lecture session 11.0 in "Garden Foyer" 1320 - 1350 Lunch Break in the Garden Foyer On all conference days (Tuesday to Thursday), a buffet lunch will be offered in the Garden Foyer, in front of the session rooms. Kindly note that this is restricted to conference delegates possessing a lunch voucher only. When entering the lunch break area, delegates will be asked to present the corresponding lunch voucher of the day. Once the lunch area is being left, re-entrance is not allowed for the respective lunch.

Time

Label

Presentation Title
Authors

11:00

10.5.1

MACHINE LEARNING ENABLED POWER-AWARE NETWORK-ON-CHIP DESIGN
Speaker:
Avinash Kodi, Ohio University, US
Authors:
Dominic DiTomaso¹, Ashif Sikder¹, Avinash Kodi¹ and Ahmed Louri²
¹Ohio University, US; ²George Washington University, US
Abstract
Although Network-on-Chips (NoCs) are fast becoming pervasive as the interconnect fabric for multicore architectures and systems-on-chips, they still suffer from excessive static and dynamic power consumption. High dynamic power consumption results from switching and storing data within routers/links while excess static power is consumed when routers and links are not utilized for communication and yet have to be powered up. In this paper, we propose LESSON (Learning Enabled Sleepy Storage Links and Routers in NoCs) to reduce both static and dynamic power consumption by power-gating the links and routers at low network utilization and moving the data storage from within the routers to the links at high network utilization. As the network utilization increases from low-to-high, to accommodate more traffic, we design the same channels to flow traffic in either direction, thereby avoiding complex routing or look-ahead wake-up algorithms. Machine learning algorithms predict when to power-gate the channels and routers and when to increase the channel bandwidths such that power savings are maximized while performance penalty is minimized. Our results show that we can improve total network power consumption when compared to conventional NoC buffer designs by 85.6% and when compared with aggressive NoC buffer designs by 31.7%. Our predictor shows marginal performance penalties and by dynamically changing the direction of the links, we can improve packet latency by 14%.
Download Paper (PDF; Only available from the DATE venue WiFi)

11:30

10.5.2

PERFORMANCE EVALUATION AND DESIGN TRADE-OFFS FOR WIRELESS-ENABLED SMART NOC
Speaker:
Karthi Duraisamy, Washington State University, US
Authors:
Karthi Duraisamy and Partha Pande, Washington State University, US
Abstract
SMART (Single-Cycle Multi-hop Asynchronous Repeated Traversal) NoC architectures enable single cycle data transfers, even between the physically far apart nodes. However, enabling single cycle hops over long distance restricts the achievable clock frequency of the system. In other words, increasing the NoC clock frequency lowers the number of hops that can be traversed in a single-cycle in a conventional SMART NoC. In this work, we demonstrate that by integrating wireless links and a novel look-ahead request mechanism in the SMART NoC, it is possible to enable low-latency and energy efficient data transfers, even when the system is designed with high clock frequencies. For various applications considered in this work, our wireless-enabled SMART (WiSMART) NoC achieves on an average 33% reduction in message latency compared to the wireline SMART mesh NoC. This network level improvement translates into 16% savings in full system energy-delay-product.
Download Paper (PDF; Only available from the DATE venue WiFi)

12:00

10.5.3

ROBUST TSV-BASED 3D NOC DESIGN TO COUNTERACT ELECTROMIGRATION AND CROSSTALK NOISE
Speaker:
Partha Pande, Washington State University, US
Authors:
Sourav Das¹, Janardhan Rao Doppa¹, Partha Pande¹ and Krishnendu Chakrabarty²
¹Washington State University, US; ²Duke University, US
Abstract
A 3D network-on-chip (3D NoC) is an enabler for the design of high-performance and energy-efficient manycore chips. Most popular 3D NoCs utilize the Through-Silicon-Via (TSV)-based vertical links (VLs) as the communication pillars between the planar dies. However, the TSVs in a 3D NoC may fail due to both workload-induced stress and crosstalk capacitance. This failure negatively affects the overall achievable performance of the 3D NoC. In this work, we analyze the joint effects of workload-induced stress and crosstalk on the TSV mean-time-to-failure (MTTF) and hence the 3D NoC lifetime. We demonstrate that if we only consider the effects of electromigration on the TSVs due to workload-induced stress then the estimated MTTF and the subsequently lifetime of 3D NoC are too optimistic. Due to the combined effects of workload and crosstalk noise, the lifetime of 3D NoC reduces significantly. Subsequently, we demonstrate that a spare TSV allocation methodology considering the joint effects of workload and crosstalk noise enhances the lifetime of the 3D NoC by a factor of 4.6 compared to when only the workload is considered for a given spare budget of 5%.
Download Paper (PDF; Only available from the DATE venue WiFi)

12:15

10.5.4

PERFORMANCE AND ENERGY AWARE WAVELENGTH ALLOCATION ON RING-BASED WDM 3D OPTICAL NOC
Speaker:
Jiating Luo, INRIA/IRISA, FR
Authors:
Jiating Luo¹, Ashraf Elantably¹, Pham Van-Dung¹, Cedric Killian¹, Daniel Chillet¹, Sébastien Le Beux², Olivier Sentieys³ and Ian O'Connor²
¹INRIA/IRISA, FR; ²Lyon Institute of Nanotechnology, FR; ³INRIA, FR
Abstract
Optical Network-on-Chip (ONoC) is a promising communication medium for large-scale Multiprocessor System on Chip (MPSoC). ONoC outperforms classical electrical NoC in terms of throughput and latency. The medium can support multiple transactions at the same time on different wavelengths by using Wavelength Division Multiplexing (WDM). Moreover multiple wavelengths can be used as high-bandwidth channel to reduce transmission time. However, multiple signals sharing simultaneously a waveguide can lead to inter-channel crosstalk noise. This problem impacts the Signal to Noise Ratio (SNR) of the optical signal, which leads to an increase in the Bit Error Rate (BER) at the receiver side. In this paper we first formulate the crosstalk noise and execution time models and then propose a Wavelength Allocation (WA) method in a ring-based WDM ONoC allowing to search for performance and energy trade-offs, based on the application constraints. As result, most promising WA solutions are highlighted for a defined application mapping onto 16-core WDM ONoC.
Download Paper (PDF; Only available from the DATE venue WiFi)

12:30

End of session
Lunch Break in Garden Foyer

Keynote Lecture session 11.0 in "Garden Foyer" 1320 - 1350

Lunch Break in the Garden Foyer
On all conference days (Tuesday to Thursday), a buffet lunch will be offered in the Garden Foyer, in front of the session rooms. Kindly note that this is restricted to conference delegates possessing a lunch voucher only. When entering the lunch break area, delegates will be asked to present the corresponding lunch voucher of the day. Once the lunch area is being left, re-entrance is not allowed for the respective lunch.

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