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10.4 Emerging Architectures for Reconfigurable Computing

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Date: Thursday 30 March 2017
Time: 11:00 - 12:30
Location / Room: 3A

Chair:
Alessandro Cilardo, University of Naples Federico II, IT

Co-Chair:
Florent de Dinechin, ENS-Lyon, FR

This session presents a view of future reconfigurable architectures. These include a field programmable transistor array, a programmable methodology for power gating FPGA routing network, and a dynamic instruction issue technique for coarse grain reconfigurable architectures.

TimeLabelPresentation Title
Authors
11:0010.4.1(Best Paper Award Candidate)
A FIELD PROGRAMMABLE TRANSISTOR ARRAY FEATURING SINGLE-CYCLE PARTIAL/FULL DYNAMIC RECONFIGURATION
Speaker:
Carl Sechen, The University of Texas at Dallas, US
Authors:
Jingxiang Tian, Gaurav Rajavendra Reddy, Jiajia Wang, William Swartz Jr., Yiorgos Makris and Carl Sechen, The University of Texas at Dallas, US
Abstract
We introduce a CMOS computational fabric consisting of carefully arranged regular rows and columns of transistors which can be individually configured and appropriately interconnected in order to implement a target digital circuit. Termed Field Programmable Transistor Array (FPTA), this novel reconfigurable architecture enables several highly-desirable features including (i) simultaneous storage of three configurations along with the ability to dynamically switch between them within a single cycle, while retaining the fabric's computational state, (ii) rapid partial or full modification of a stored configuration in a time proportional to the number of modified configuration bits through the use of hierarchically-arranged, high-throughput, asynchronously pipelined memory buffers, and (iii) support for libraries containing cells of the same height and variable width, just as in a typical standard cell circuit, thereby simplifying transition from a prototype to a custom IC design. Besides presenting the design details of this fabric in a 130nm technology and demonstrating the aforementioned capabilities, we also briefly discuss the development of a complete CAD flow for programing this fabric and we use numerous benchmark circuits to contrast its area efficiency against a typical FPGA implemented in the same technology node.
Download Paper (PDF; Only available from the DATE venue WiFi)
11:3010.4.2A POWER GATING SWITCH BOX ARCHITECTURE IN ROUTING NETWORK OF SRAM-BASED FPGAS IN DARK SILICON ERA
Speaker:
Hossein Asadi, Sharif University of Technology, IR
Authors:
Zeinab Seifoori, Behnam Khaleghi and Hossein Asadi, Sharif University of Technology, IR
Abstract
Continuous down scaling of CMOS technology in recent years has resulted in exponential increase in static power consumption which acts as a power wall for further transistor integration. One promising approach to throttle the substantial static power of Field-Programmable Gate Array (FPGAs) is to power off unused routing resources such as switch boxes, known as dark silicon. In this paper, we present a Power gating Switch Box Architecture (PESA) for routing network of SRAM-based FPGAs to overcome the obstacle for further device integration. In the proposed architecture, by exploring various patterns of used multiplexers in switch boxes, we employ a configurable controller to turn off unused resources in the routing network. Our study shows that due to the significant percentage of unused switches in the routing network, PESA is able to considerably improve power efficiency in SRAM-based FPGAs. Experimental results carried out on different benchmarks using VPR toolset show that PESA decreases power consumption of the routing network up to 75% as compared to the conventional architectures while preserving the performance intact.
Download Paper (PDF; Only available from the DATE venue WiFi)
12:0010.4.3A STATIC-PLACEMENT, DYNAMIC-ISSUE FRAMEWORK FOR CGRA LOOP ACCELERATOR
Speaker:
Zhongyuan Zhao, Department of NaNo/Micro Electronics, CN
Authors:
Zhongyuan Zhao1, Weiguang Sheng1, Weifeng He1, Zhigang Mao1 and Zhaoshi Li2
1Shanghai JiaoTong University, CN; 2Tsinghua University, Beijing, CN
Abstract
This paper presents a static-placement, dynamic issue (SPDI) framework for the coarse-grained reconfigurable architecture (CGRA) in order to tackle the inefficiencies of the static-issue, static-placement (SISP) CGRA. This framework includes the compiler that statically places the operations and hardware design, a SPDI CGRA, that automatically schedule the operations. We stress on introducing the SPDI CGRA in this paper. This newly designed hardware model adds the token buffer, which is capable of automatically scheduling the operations inside processing elements (PE), along with a router network that can effectively transform and control data flow among the PE array. This design lets the hardware share the responsibility for the compiler, making them cooperate to deal with the issuing, placement and routing problem. Evaluation of our study shows that our framework can reach on average 1.28, 1.30 and 1.33 higher than three state-of-the-art SISP CGRA using REGIMap, RS compile flow and the EPIMap approaches respectively. The area overhead is nearly 0.93% per token buffer entry for each PE relative to SISP CGRA.
Download Paper (PDF; Only available from the DATE venue WiFi)
12:30End of session
Lunch Break in Garden Foyer

Keynote Lecture session 11.0 in "Garden Foyer" 1320 - 1350

Lunch Break in the Garden Foyer
On all conference days (Tuesday to Thursday), a buffet lunch will be offered in the Garden Foyer, in front of the session rooms. Kindly note that this is restricted to conference delegates possessing a lunch voucher only. When entering the lunch break area, delegates will be asked to present the corresponding lunch voucher of the day. Once the lunch area is being left, re-entrance is not allowed for the respective lunch.

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