Date: Tuesday 15 March 2016
Time: 10:30 - 12:30
Location / Room: Booth 15, Exhibition Area
| Label | Presentation Title Authors |
|---|---|
| UB01.1 | HIGH-END 122GHZ MINIATURE RADAR SENSOR FOR AUTONOMOUS AIRCRAFTS Presenter: Federico Nava, Heinz Nixdorf Institute - Universität Paderborn, DE Authors: Federico Nava1 and Christoph Scheytt2 1Heinz Nixdorf Institute - Universität Paderborn, DE; 2Heinz Nixdorf Institute - Paderborn, DE Abstract The importance of high precision sensors, sensors-arrays and the concept of sensor fusion are rising interest in the field of scientific research for autonomous vehicles. For this reason the System and Circuit Technology group at the Heinz Nixdorf Institute is currently developing a highly integrated radar module as a sensor for Unmanned Aerial Vehicle applications. The presented system is composed of a radar IC (130nm SiGe) with in-package antennas and operating frequency of 122GHz mounted on a FLEX-PCB including a CORTEX M4 MCU for a total size of 30x30mm. The presentation will show the FMCW/CW radar functions of the device, allowing the tracking of velocity and distance for multiple objects. The results of the radar measurements will be presented on a screen showing the raw data acquired in time domain and a FFT representation. Different objects will move simultaneously in the area of reception of the sensor. The results of the tracked distances will be then plotted on screen. Download Paper (PDF) |
| UB01.2 | D-VASIM: TIMING ANALYSIS OF GENETIC LOGIC CIRCUITS USING D-VASIM Presenter: Hasan Baig, Technical University of Denmark, DK Authors: Hasan Baig and Jan Madsen, Technical University of Denmark, DK Abstract A genetic logic circuit is a gene regulator network implemented by re-engineering the DNA of a cell, in order to control gene expression or metabolic pathways, through a logic combination of external signals, such as chemicals or proteins. As for electronic logic circuits, timing and propagation delay analysis may also play a very significant role in the designing of genetic logic circuits. In this demonstration, we present the capability of D-VASim (Dynamic Virtual Analyzer and Simulator) to perform the timing and propagation delay analysis of a single as well as cascaded genetic logic circuits. D-VASim allows user to change the circuit parameters during runtime simulation to observe their effects on circuit's timing behavior. The results obtained from D-VASim can be used not only to characterize the timing behavior of genetic logic circuits but also to analyze the timing constraints of cascaded genetic logic circuits. Download Paper (PDF) |
| UB01.3 | ALPT: A FAST PROTOTYPING METHODOLOGY WITH CONSTRAINED FLOORPLANING ON ANALOG LAYOUT GENERATION Presenter: Po-Cheng Pan, National Chiao Tung University, TW Authors: Po-Cheng Pan, Hung-Wen Huang and Hung-Ming Chen, National Chiao Tung University, TW Abstract Layout generation in the recent analog design is challenging by its critical layout dependent effect (LDE). Based on the same netlist design, different layouts lead distinct performances. Therefore, it is necessary to observe and avoid the LDE during generation. Traditionally, the strategies of analog layout generation mostly count on experienced designers. However, the experience is based on time-consuming manually try-run, which is inefficient and unreliable. In this work, we develop a fast prototyping for analog layout generation. In our approach, we apply a fast floorplanning algorithm, for multi-layout generation and select the feasible results w.r.t. the analog constraints pre-decided. For practical usage, we implement this approach embedded on the EDA-tool so that layout designers are able to design with such prototypes for efficiency. The demonstration includes layout prototyping generation, the integration between our program and EDA-tool and the resulting layout prototypes. Download Paper (PDF) |
| UB01.4 | MICROTESK ARMV8 EDITION: SPECIFICATION-BASED TEST PROGRAM GENERATOR Presenter: Andrei Tatarnikov, Russian Academy of Sciences (RAS), RU Authors: Andrei Tatarnikov, Alexander Kamkin and Artem Kotsynyak, Russian Academy of Sciences (RAS), RU Abstract This work presents a test program generation tool for ARMv8 microprocessors. The tool consists of two parts: an architecture-independent test program generation core and ARMv8 specifications. The specifications provide information on the instruction set architecture and the memory management unit of an ARMv8 microprocessor. Test programs are generated on the basis of test templates provided by users and testing knowledge extracted from the specifications. Test templates describe scenarios to be covered in terms of test situations, while testing knowledge specifies constraints that should be satisfied in order for these situations to occur. The architecture-independent test program generation core implements a wide range of test generation techniques including random generation, combinatorial generation, constraint solving and symbolic execution. Flexible architecture of the tool allows integrating different generation methods and extending the test generation core with new engines. Download Paper (PDF) |
| UB01.5 | AGAMID: A TLM FRAMEWORK FOR EVALUATION OF HARDWARE-ENHANCED MANY-CORE RUN-TIME MANAGEMENT Presenter: Daniel Gregorek, University of Bremen, DE Authors: Daniel Gregorek and Alberto Garcia-Ortiz, University of Bremen, DE Abstract The advent of many-core processors raises novel demands to system design. Power-limitations and abundant parallelism require for efficient and scalable run-time management. But the design of a many-core run-time manager generally suffers from exhaustive evaluation time. AGAMID is a novel research framework for design space exploration of hardware-enhanced many-core run-time management. In this demo, we use AGAMID for the interactive analysis of many-core architectures and run-time management systems. We perform hands-on comparison of RTM architectures, RTM algorithms and HW/SW partitionings. We also give insights into the design and architecture of the framework itself. Download Paper (PDF) |
| UB01.6 | A-LOOP: AMP SYSTEM WITH A DUAL-CORE ARM CORTEX A9 PROCESSOR WITH LINUX OPERATING SYSTEM AND A QUAD-CORE LEON3 PROCESSOR WITH LINUX OPERATING SYSTEM, OPENMP LIBRARY AND HARDWARE PROFILING SYSTEM Presenter: Giacomo Valente, Università Degli Studi Dell'Aquila, IT Authors: Giacomo Valente and Vittoriano Muttillo, Università Degli Studi Dell'Aquila, IT Abstract Isles of computational elements with different characteristics can be exploited for separate tasks with different non-functional requirements. This can drive to realization of smart System On Modules (SoM). In such a context, SoC with FPGA can be viewed as platforms useful to prototype these architectures. This demo shows a SoM prototype for aerospace applications developed on Zynq7000 SoC, composed of dual-core ARM Cortex A9 with Linux operating system (isle#1) able to interface with external data, and quad-core Leon3 with SMP Linux operating system (isle#2), able to execute parallel applications based on OpenMP library. These 2 computational isles share an external DDR memory, so that isle#1 can provide data and collect results from isle#2. Moreover, isle#1 is able to monitor performance of isle#2 without introducing software overhead (i.e. no SW instrumentation) by using a hardware profiling system. The whole system that executes a MANET localization algorithm will be presented. Download Paper (PDF) |
| UB01.7 | RETRASCOPE: TOOLKIT FOR ANALYSIS AND VERIFICATION OF HDL DESIGNS Presenter: Sergey Smolov, Russian Academy of Sciences (RAS), RU Authors: Sergey Smolov, Alexander Kamkin and Mikhail Lebedev, Russian Academy of Sciences (RAS), RU Abstract Retrascope is an open-source toolkit for Reverse Engineering and TRAnsformation of digital hardware designs described in such hardware description languages as Verilog and VHDL. The toolkit allows analyzing HDL descriptions, reconstructing the underlying models (guarded actions, extended finite state machines, high-level decision diagrams etc.) and using the derived models for test generation, property checking and other tasks. Retrascope is organized as an extendible framework with the ability to add new types of models as well as tools for their analysis and transformation. The primary application domain of the toolkit is functional verification of hardware at the unit level. Download Paper (PDF) |
| UB01.8 | PFPSIM: A PROGRAMMABLE FORWARDING PLANE SIMULATOR Presenter: Gordon Bailey, Concordia University, CA Author: Gordon Bailey, Concordia University, CA Abstract We demonstrate PFPSim, a host-compiled simulator for early validation and analysis of packet processing applications on programmable forwarding plane architectures, used in software defined networks. The simulation model is automatically generated from a high-level description of the hardware/software architecture of the forwarding device and the behavioral description of the various modules in the architecture. Our high-level architectural description language is capable of defining many-core network processors as well as reconfigurable pipelines. The behavior of the fixed-function processing elements in the architecture is defined in C++. The code targeted for the processor cores, or reconfigurable pipeline stages, is compiled from P4, an emerging programming language for packet processing applications. Network dataplane programmers can use PFPSim as a virtual prototype to simulate and debug their applications before hardware availability. Download Paper (PDF) |
| UB01.9 | BIOVIZ: AN INTERACTIVE VISUALIZATION ENGINE FOR MICROFLUIDIC BIOCHIPS Presenter: Oliver Keszöcze, University of Bremen, DE Authors: Oliver Keszöcze1, Jannis Stoppe2, Robert Wille3 and Rolf Drechsler2 1University of Bremen, DE; 2DFKI and University of Bremen, DE; 3Johannes Kepler University, AT, DFKI and University of Bremen, DE Abstract In order to shorten the required time for the analysis of medical substances, digital microfluidic biochips (DMFBs) have been suggested. Issues such as routing and layouting are complex and currently being investigated. Although first automatic solutions assist the designers, the results are usually provided in a complex and non-intuitive fashion. Creating solutions requires testing of different setups, comparing the results and debugging of algorithms. Solutions, while being technically correct, often include negative aspects such as e.g. unnecessary cell usage. These aspects are difficult to spot without being able to visually inspect the design. Still, while designers would benefit from visualization tools, no dedicated tools have been built yet. We present BioViz, an interactive visualization tool for DMFBs that explicitly addresses these problems. Download Paper (PDF) |
| 12:30 | End of session |
| 13:00 | Lunch Break in Großer Saal + Saal 1 |