Date: Wednesday 16 March 2016
Time: 17:00 - 18:30
Location / Room: Konferenz 2
Chair:
Fabian Oboril, KIT Germany, DE
Co-Chair:
Luciano Lavagno, Politecnico di Torino, IT
Techniques such as machine learning, spiking neural networks, and probabilistic analysis are being adopted in advanced high-level design methods. This session presents a sampling of these topics, and concludes with a short IP presentation on a new approach to predicting reusable hardware.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 17:00 | 8.4.1 | ADAPTIVE THRESHOLD NON-PARETO ELIMINATION: RE-THINKING MACHINE LEARNING FOR SYSTEM LEVEL DESIGN SPACE EXPLORATION ON FPGAS Speaker: Pingfan Meng, University of California, San Diego, US Authors: Pingfan Meng, Alric Althoff, Quentin Gautier and Ryan Kastner, University of California, San Diego, US Abstract One major bottleneck of the system level OpenCL-to-FPGA design tools is their extremely time consuming synthesis process (including placement and route). The design space for a typical OpenCL application contains thousands of possible designs even when considering a small number of design space parameters. It costs months of compute time to synthesize all these possible designs into end-to-end FPGA implementations. Thus, the brute force design space exploration (DSE) is impractical for these design tools. Machine learning is one solution that identifies the valuable Pareto designs by sampling only a small portion of the entire design space. However, most of the existing machine learning frameworks focus on improving the design objective regression accuracy, which is not necessarily suitable for the FPGA DSE task. To address this issue, we propose a novel strategy - Adaptive Threshold Non-Pareto Elimination (ATNE). Instead of focusing on regression accuracy improvement, ATNE focuses on understanding and estimating the inaccuracy. ATNE provides a Pareto identification threshold that adapts to the estimated inaccuracy of the regressor. This adaptive threshold results in a more efficient DSE. For the same prediction quality, ATNE reduces the synthesis complexity by 1.6 - 2.89X (hundreds of synthesis hours) against the other state of the art frameworks for FPGA DSE. In addition, ATNE is capable of identifying the Pareto designs for certain difficult design spaces which the other existing frameworks are incapable of exploring effectively. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 17:30 | 8.4.2 | MONITORING OF MTL SPECIFICATIONS WITH IBM'S SPIKING-NEURON MODEL Speaker: Konstantin Selyunin, Vienna University of Technology, AT Authors: Konstantin Selyunin1, Thang Nguyen2, Ezio Bartocci1, Dejan Nickovic3 and Radu Grosu1 1Vienna University of Technology, AT; 2Infineon Technologies Austria AG, AT; 3AIT Austrian Institute of Technology, AT Abstract This paper shows how to use the IBM's TrueNorth spiking neuron model, for monitoring if a digital signal satisfies a metric temporal-logic (MTL) specification. TrueNorth spiking neurons are universal computation blocks, which can perform a variety of deterministic or stochastic tasks (e.g., Boolean/arithmetic opera- tions, filtering, and convolution) depending on the configuration of their parameters. We show how to set these parameters for the deterministic TrueNorth neural-model in order to recognize MTL operators. A TrueNorth circuit then behaves as a runtime MTL monitor. We demonstrate how to translate the neural monitor to synthesizable HDL-code on Xilinx's Zedboard using high-level synthesis. To the best of our knowledge, this is the first application of the IBM's TrueNorth model for runtime monitoring. It also demonstrates the complete flow from a high- level specification to the implementation of a neural monitor in FPGA. As a byproduct, the paper also introduces the first open- source FPGA implementation of the deterministic TrueNorth model. We demonstrate the usefulness of our approach on a case study, the launching of a missile from a battle ship. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 18:00 | 8.4.3 | FORMAL PROBABILISTIC ANALYSIS OF DISTRIBUTED RESOURCE MANAGEMENT SCHEMES IN ON-CHIP SYSTEMS Speaker: Osman Hasan, School of Electrical Engineering and Computer Science (SEECS), NUST, PK Authors: Shafaq Iqtedar1, Osman Hasan1, Muhammad Shafique2 and Jörg Henkel2 1National University of Sciences and Technology (NUST), PK; 2Karlsruhe Institute of Technology (KIT), DE Abstract New paradigms for managing resources in on-chip many-core systems come with various issues, among them is the key demand for robust verification of (distributed) resource management schemes before deployment. Moreover, it is important to have a unified framework where different resource management schemes can be formally analyzed and compared for their performance efficiency and robustness. Traditional techniques, like simulation or emulation, are inherently in-exhaustive and thus compromise the completeness and accuracy of the analysis results. In this work, we present a formal approach, based on probabilistic model checking, for evaluating and comparing the performance of different distributed resource management schemes. To illustrate the benefits and applicability of our formal verification and comparative analysis approach, we perform a case study on the comparison of two recent state-of-the-art distributed resource management schemes using the PRISM model checker. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 18:30 | IP4-1, 927 | A Q-GRAM BIRTHMARKING APPROACH TO PREDICTING REUSABLE HARDWARE Speaker: Kevin Zeng, Virginia Tech, US Authors: Kevin Zeng and Peter Athanas, Virginia Tech, US Abstract Designer productivity is a growing concern as overall hardware complexity rises. Design reuse, a key component in productivity, is underutilized. Not only can existing designs be reused, but also the patterns and information contained within them as well. With the increase in the number of circuits available, there requires a need to analyze and retrieve designs with ease in order to accelerate design entry. In this paper, a birthmarking approach using q-grams is presented. Using this technique, design patterns regarding existing circuits can be captured and used to not only suggest similar and reusable designs, but functional blocks throughout the design phase, with little to no effort from the user. Preliminary experiments and case studies of the q-gram birthmarking technique were performed on over 250 circuits from various sources in order to show the feasibility of the proposed methods. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 18:30 | End of session | |