Date: Wednesday 16 March 2016
Time: 11:00 - 12:30
Location / Room: Konferenz 5
Chair:
Viacheslav Izosimov, Semcon Sweden AB, SE
Co-Chair:
Zebo Peng, Linköping University, SE
The papers in this session present arithmetic components for approximate and fault tolerant computing, self-checking methodologies and tools for the implementation and evaluation of reliable systems
| Time | Label | Presentation Title Authors |
|---|---|---|
| 11:00 | 6.7.1 | (Best Paper Award Candidate) INEXACT DESIGNS FOR APPROXIMATE LOW POWER ADDITION BY CELL REPLACEMENT Speaker: Nandha Kumar Thulasiraman, The University of Nottingham, MY Authors: Haider A.F. Almurib1, Nandha Kumar Thulasiraman1 and Fabrizio Lombardi2 1The University of Nottingham, MY; 2Northeastern University, US Abstract This paper proposes three designs of an inexact adder cell for approximate computing. These cells require a substantially smaller number of transistors compared to an exact full adder cell as well as known inexact designs. These inexact cells are simulated at 45 nm and compared with respect to circuit based metrics (such as energy consumption, delay, complexity and energy delay product) as well as error metrics (such as error rate). The replacement of exact cells with inexact cells such as the ones proposed in this manuscript in a ripple carry adder is evaluated to assess by exhaustive simulation different metrics for approximate computing; image addition is then pursued as application. These results show that among existing inexact cells found in the technical literature, the proposed designs consume the least power and have superior performance in terms of delay, switching capacitance and error measures for image quality and processing. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 11:30 | 6.7.2 | A GENERAL APPROACH FOR HIGHLY DEFECT TOLERANT PARALLEL PREFIX ADDER DESIGN Speaker: Wenjing Rao, University of Illinois at Chicago, US Authors: Soumya Banerjee and Wenjing Rao, University of Illinois at Chicago, US Abstract This paper proposes a highly defect tolerant Parallel Prefix Adder (PPA) design. Motivated by the inherent defect tolerance capability displayed in a Kogge Stone Adder (KSA), this paper identifies the key elements that can be applied to make the general PPA's defect tolerant: 1) the Generate and Propagate computing hardware is divided into disjoint groups, such that defects in one group will not "contaminate" the computation carried out by the other groups; 2) redundant copies of the results for each group can be derived cost-effectively from the other disjoint groups. This approach provides flexibilities for a defect tolerant PPA design on both the number of groups and the type of Sub-Adder structure to be adopted. As is verified by the simulation results, the proposed scheme not only offers a general way of constructing highly defect tolerant PPA's, but also opens up a large number of pareto-front design choices, considering the objectives of reliability, hardware and performance. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 12:00 | 6.7.3 | INVERTERS' SELF-CHECKING MONITORS FOR RELIABLE PHOTOVOLTAIC SYSTEMS Speaker: Cecilia Metra, Università di Bologna, IT Authors: Martin Omana, Alessandro Fiore and Cecilia Metra, Università di Bologna, IT Abstract Photovoltaic systems are a widespread form of green energy, that is becoming increasingly considered also as a form of economical investment. Their reliability is consequently becoming a concern. In this paper we focus on the reliability of the DC-AC converters (inverters) of photovoltaic (PV) systems. We analyze the effects of the faults likely to affect their operation in the field. We show that such faults can impact catastrophically the power delivered to the load. We then propose a self-checking monitor, that is able to detect the occurrence of such faults in the field, as well as faults possibly affecting itself. Our monitor can therefore be adopted to guarantee the concurrent on-line test of faults affecting the inverters of PV systems. Moreover, if used together with suitable recovery strategies, for instance based on proper hardware reconfiguration, it can provide PV systems with fault tolerance ability, thus meeting the increasing demand for reliable PV systems. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 12:30 | IP3-5, 327 | TOWARDS LOW OVERHEAD CONTROL FLOW CHECKING USING REGULAR STRUCTURED CONTROL Speaker: Zhiqi Zhu, The University of Texas at Dallas, US Authors: Zhiqi Zhu and Joseph Callenes-Sloan, The University of Texas at Dallas, US Abstract Abstract—With process scaling and the adoption of post- CMOS technologies, reliability has been brought to the forefront of modern computer system design. Among the different ways that hardware faults can manifest in a system, errors related to the control flow of a program tend to be the most difficult to handle when ensuring reliable computing. Errors in the sequencing of instructions executed are usually catastrophic, resulting in system hangs, crashes, and/or corrupted data. For this reason, conventional approaches rely on some form of general redundancy for detecting or recovering from a control flow error. Due to the power constraints of emerging systems however, these types of conservative approaches are quickly becoming infeasible. Control Flow Checking by Software Signatures (CFCSS) is a software-based technique for detecting control flow errors [1] that using assigned signatures rather than by using general redundancy. Unfortunately, the performance overhead for CFCSS can still be as high as 80%-90% for many applications. In this paper, we propose a novel method for reducing the overhead of control flow checking by exploiting the regular control structure found in many applications. Specifically, we observe that the alternating sequence of conditional and unconditional based control allows for the full control signatures to be computed at alternating basic blocks. Based on experimental results of the proposed approach, we observe that the overheads of the traditional methods are reduced on average by 25.9%. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 12:31 | IP3-6, 460 | EMULATION-BASED HIERARCHICAL FAULT-INJECTION FRAMEWORK FOR COARSE-TO-FINE VULNERABILITY ANALYSIS OF HARDWARE-ACCELERATED APPROXIMATE ALGORITHMS Speaker: Theocharis Theocharides, University of Cyprus, CY Authors: Ioannis Chadjiminas, Ioannis Savva, Christos Kyrkou, Maria K. Michael and Theocharis Theocharides, University of Cyprus, CY Abstract This paper proposes a hierarchical fault injection emulation framework tailored to the structure of complex and large application-specific circuits, that performs vulnerability analysis of the system for single event upsets (SEUs) at different design granularities in real-time. In particular, the framework allows for efficient probabilistic modelling of the SEU impact, making it particularly applicable for hardware-accelerated approximate applications such as multimedia, computer vision and image/signal processing, due to its high processing speed and real-time capabilities. The framework is emulated on an FPGA-based platform and evaluated using a depth computation kernel, both in standalone manner as well as within a robotic obstacle avoidance application. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 12:30 | End of session Lunch Break in Großer Saal + Saal 1 Keynote Lecture in "Saal 2" 14:00 - 14:30 |