Date: Thursday 17 March 2016
Time: 14:00 - 15:30
Location / Room: Konferenz 5
Chair:
Árpád Bürmen, University of Ljubljana, SI
Co-Chair:
Francisco Fernandez, IMSE-CNM, ES
The first paper introduces exciting Boolean methods into analog layout design. The second paper shows how to boost circuit optimization by data mining. The third paper presents a cocktail of model-based and simulation-based optimization. Two IPs complete the session with parallelization and learning in synthesis.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 14:00 | 11.7.1 | (Best Paper Award Candidate) PARETO FRONT ANALOG LAYOUT PLACEMENT USING SATISFIABILITY MODULO THEORIES Speaker: Sherif Saif, Electronics Research Institute, EG Authors: Sherif Saif1, Mohamed Dessouky2, M. Watheq El-Kharashi3, Hazem Abbas4 and Salwa Nassar1 1Electronics Research Institute, EG; 2Mentor Graphics Corporation, EG; 3Faculty of Engineering, Ain Shams University, EG; 4Faculty of Media Engineering & Technology, GUC, EG Abstract This paper presents an analog layout placement tool with emphasis on Pareto front generation. In order to handle the exploding number of analog physical constraints, a new approach based on the use of a Satisfiability Modulo Theories (SMT) solver is suggested. SMT is an area concerned with checking the satisfiability of logical formulas over one or more theories. SMT is usually well-tuned to solve specific problems. To our knowledge, this is the first effort to use SMT to tackle analog placement. The proposed tool implicitly generates multiple layouts that fulfill the given constraints. Therefore, it gives the user the option to choose from the feasible solutions through specifying an aspect ratio or by selecting the optimum solution from the Pareto front of the generated shape function. In contrast to most of the existing techniques, as the number of physical constraints increases the SMT solver processing time decreases. The proposed system yielded layouts with a competitive area and run time compared to other techniques. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 14:30 | 11.7.2 | EFFICIENT MULTIPLE STARTING POINT OPTIMIZATION FOR AUTOMATED ANALOG CIRCUIT OPTIMIZATION VIA RECYCLING SIMULATION DATA Speaker: Bo Peng, Fudan University, CN Authors: Bo Peng, Fan Yang, Changhao Yan, Xuan Zeng and Dian Zhou, Fudan University, CN Abstract Multiple starting point optimization is an efficient approach for automated analog circuit optimization. Starting from a set of starting points, the corresponding local optimums are reached by local optimization method Sequential Quadratic Programming (SQP). The global optimum is then selected from these local optimums. If one starting point is located in a valley, it converges rapidly to the local optimum by the local search. Such a region-hit property makes the multiple starting optimization approach more likely to reach the global optimum. However, the SQP method needs the gradients to drive the optimization. In the traditional method, the gradients are approximated by finite differences. A large number of simulations are needed to obtain the gradients, which becomes the bottleneck of the circuit optimization. We find that for a new point, it is usually surrounded by several neighboring points which have been evaluated in the previous SQP steps. In this paper, we propose an efficient method to calculate the gradient by recycling the previous evaluated points. It is based on the relationship between gradients and the directional derivatives along the directions of the neighbor points. If the neighboring points are not enough for gradient calculation, we will sample adequate neighboring points for gradient calculation. Furthermore, since the performances of the circuits are not sensitive to some design parameters, the gradients are usually sparse. We can thus further employ the idea of sparse recovery to recover the sparse gradients with fewer simulations. Our experimental results demonstrate that with these strategies, the number of simulations can be reduced by up to 63\% without significantly surrendering the accuracy of the optimization results. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 15:00 | 11.7.3 | POLYGP: IMPROVING GP-BASED ANALOG OPTIMIZATION THROUGH ACCURATE HIGH-ORDER MONOMIALS AND SEMIDEFINITE RELAXATION Speaker: Ye Wang, The University of Texas at Austin, US Authors: Ye Wang, Michael Orshansky and Constantine Caramanis, The University of Texas at Austin, US Abstract Geometric programming (GP) is popular for use in equation-based optimization of analog circuits thanks to GP-compatible analog performance functions, and its convexity, hence computational tractability. The main challenge in using GP, and thus a roadblock to wider use and adoption, is the mismatch between what GP can accurately fit, and the behavior of many common device/circuit functions. In this paper, we leverage recent tools from sums-of-squares, moment optimization, and semidefinite optimization (SDP), in order to present a novel and powerful extension to address the monomial inaccuracy: fitting device models as higher-order monomials, defined as the exponential functions of polynomials in the logarithmic variables. By the introduction of high-order monomials, the original GP problems become polynomial geometric programming (PolyGP) problems with non-linear and non-convex objective and constraints. Our PolyGP framework allows significant improvements in model accuracy when symbolic performance functions in terms of device models are present. Via SDP-relaxations inspired by polynomial optimization (POP), we can obtain efficient near-optimal global solutions to the resulting PolyGP. Experimental results through established circuits show that compared to GP, we are able to reduce fitting error of device models to 3.5% from 10.5% on average. Hence, the fitting error of performance functions decrease from 12% of GP and 9% of POP, to 3% accordingly. This translates to the ability of identifying superior solution points and the dramatic decrease of constraint violation in contrast to both GP and POP. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 15:30 | IP5-21, 923 | ANALOG CIRCUIT TOPOLOGICAL FEATURE EXTRACTION WITH UNSUPERVISED LEARNING OF NEW SUB-STRUCTURES Speaker: Alex Doboli, Stony Brook University, US Authors: Hao Li, Fanshu Jiao and Alex Doboli, Stony Brook University, US Abstract This paper presents novel techniques to automatically extract the topological (structural) features in analog circuits. The extracted features include basic building blocks, structural templates and hierarchical structures. Finding structural features is important for tasks like circuit synthesis and sizing, design verification, design reuse, and design knowledge description, summarization and management. The paper presents algorithms for supervised feature extraction and unsupervised learning of new block connections. Experiments discuss feature extraction for a set of 34 state-of-the-art analog circuits. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 15:31 | IP5-22, 860 | DESIGN AUTOMATION TASKS SCHEDULING FOR ENHANCED PARALLEL EXECUTION OF A STATE-OF-THE-ART LAYOUT-AWARE SIZING APPROACH Speaker: Nuno Horta, Instituto de Telecomunicações/Instituto Superior Técnico, PT Authors: David Neves, Ricardo Martins, Nuno Lourenço and Nuno Horta, Instituto de Telecomunicações/Instituto Superior Técnico, PT Abstract This paper presents an innovative methodology to efficiently schedule design automation tasks during the execution of an analog IC layout-aware sizing process. The referred synthesis process includes several sub-tasks such as DC simulation, floorplanning, placement, global routing, parasitic extraction, and circuit simulations in multiple worst case corners. The schedule of the design tasks is here optimized taking into account standard multi-core architectures, tasks dependencies, accurate time estimations for each task and a limited number of licenses for using commercial tools, e.g., number of simulator licenses. The proposed methodology, first, considers a directed acyclic graph for representing the design flow and task dependencies, then, an evolutionary kernel is used to implement a single-objective multi-constraint optimization. The efficiency and impact of the proposed approach is validated by using a state-of-the-art Analog IC design automation environment. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 15:30 | End of session Coffee Break in Exhibition Area |