Download handouts here (Handouts are available for attendees only! The password has been sent to you by email or you may ask for the password at the on-site registration desk.)
Gabriela Nicolescu, Polytechnique Montréal, CA (Contact Gabriela Nicolescu)
Jiang Xu, Hong Kong University of Science and Technology, CN (Contact Jiang Xu)
Sébastien Le Beux, Lyon Institute of Nanotechnology, Ecole Centrale de Lyon, FR (Contact Sébastien Le Beux)
Mahdi Nikdast, Polytechnique Montréal/McGill University, CA (Contact Mahdi Nikdast)
Akihiko Shinya, NTT Basic Research Lab., JP (Contact Akihiko Shinya)
Alan Mickelson, University of Colorado at Boulder, US (Contact Alan Mickelson)
Ayse Coskun, Boston University, US (Contact Ayse Coskun)
Davide Bertozzi, University of Ferrara, IT (Contact Davide Bertozzi)
Ian O'Connor, Lyon Institute of Nanotechnology, FR (Contact Ian O'Connor)
Jiang Xu, Hong Kong University of Science and Technology, CN (Contact Jiang Xu)
Josè Flich, Universidad Politecnica de Valencia, ES (Contact Josè Flich)
Sebastien Rumley, University of Columbia, US (Contact Sebastien Rumley)
Mahdi Nikdast, Polytechnique Montréal/McGill University, CA (Contact Mahdi Nikdast)
Marc Seifried, IBM Research Lab., Zurich, CH (Contact Marc Seifried)
Nikos Hardavellas, Northwestern University, US (Contact Nikos Hardavellas)
Olivier Sentieys, INRIA - University of Rennes 1, FR (Contact Olivier Sentieys)
Isabella Cerutti, Scuola Superiore Sant'Anna, IT (Contact Isabella Cerutti)
Ruping Cao, Mentor Graphics Corp, FR (Contact Ruping Cao)
Sebastien Cremer, STMicroelectronics, FR (Contact Sebastien Cremer)
Yoan Léger, CNRS – FOTON, FR (Contact Yoan Léger)
Multiprocessor System-on-Chip (MPSoC) is becoming the standard for high-performance computing systems. The performance of an MPSoC is determined not only by the performance of its processing cores and memories, but also by how efficiently they collaborate with one another. As the technology advances and allows the integration of many processing cores, metallic interconnects in MPSoCs will consume significant power while imposing high latency and low bandwidth. Shifting to the many-core era necessitates considering an alternative interconnect technology to replace the traditional electrical interconnects. Among such technologies, photonic technology has demonstrated promising potentials to address the aforementioned issues with the metallic interconnects in MPSoCs. In this context, high-performance silicon photonic devices and circuits are necessary to construct photonic interconnect networks. Furthermore, it is required to explore the feasibility and performance of photonic interconnects as well as the guidelines and design requirements to realize such interconnects. OPTICS aims at discussing the most recent advances in photonic interconnects and silicon photonics for computing systems. Industry's and academia's views on the feasibility and recent progress of optical interconnects and silicon photonics will be discussed. The workshop is comprised of invited talks of the highest caliber in addition to refereed poster presentations.
You are invited to participate and submit your contributions to OPTICS. Papers should be in the standard IEEE 2-column conference format, and they should not exceed four pages in length, including all the figures, tables, and references. Your paper need to be submitted at https://easychair.org/conferences/?conf=optics2016 before the submission deadline (see below). Please select the "Short-Paper (Author)" under topics. This workshop does not require blind submissions. All submissions will undergo a peer-review process. If your paper is accepted, you will need to prepare a poster and present it at the workshop. Informal proceedings with the accepted papers will be made available at the end of the workshop. The papers presented at the DATE workshops are NOT disseminated through the official DATE proceedings or through any other formal channels, such as, for example, the IEEExplore or the ACM Digital Library.
The authors of the best-ranked papers will be invited to contribute a chapter to a book titled " Optical Interconnects for Computing Systems" that will be published by River Publishers (Confirmed).
Submission deadline: 15th November 2015 1st December 2015
Acceptance notification: 5th December 2015 15th December 2015
Camera ready: 1st February 2016
Time | Label | Session |
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08:30 | W06.1 | Introduction to OPTICS Workshop Chair: Co-Chair: |
08:40 | W06.2 | Morning Session I: What is New on the Technology Side? Chair: |
08:40 | W06.2.1 | Towards Next Generation of Silicon Photonics Technology Sebastien Cremer, STMicroelectronics, FR Abstract: https://www.dropbox.com/s/qbs0gxions2zptg/OPTICS_2016_paper_19_Sebastien... |
09:10 | W06.2.2 | Laser Integration Challenges for On-Chip Optical Interconnects Yoan Léger, CNRS – FOTON, FR Abstract: https://www.dropbox.com/s/daazf1vznj69fem/OPTICS_2016_paper_7_Yoan_Leger... |
09:30 | W06.2.3 | Electro-Optical Integration of III-V-on-Silicon for Efficient On-Chip Laser Sources Marc Seifried, IBM Research Lab., Zurich, CH Abstract: https://www.dropbox.com/s/8clp8gyv21mmfct/OPTICS_2016_paper_21_Marc_Seif... |
09:50 | W06.2.4 | Integrated Nanophotonics for fJ/bit On-Chip Optical Communications Akihiko Shinya, NTT Basic Research Lab., JP Abstract: https://www.dropbox.com/s/mctz8rn02mladx8/OPTICS_2016_paper_13_Akihiko_S... |
10:10 | W06.2.5 | Selective Coupling Functionalities for On-Chip Mode-Division Multiplexing Alberto Parini1, Yann Boucher2 and Christophe Peucheret3 1University of Ferrara, IT; 2OTON Laboratory, CNRS, FR; 3FOTON Laboratory, CNRS, FR Paper: https://www.dropbox.com/s/5ws9v5omzf4ilyi/OPTICS_2016_paper_3_PS1.pdf?dl=0 |
10:15 | W06.2.6 | PhoNoCMap: an Application Mapping Tool for Photonic Networks-on-Chip Edoardo Fusella and Alessandro Cilardo, University of Naples Federico II, IT Paper: https://www.dropbox.com/s/dgek42ai3svrhc5/OPTICS_2016_paper_4_PS2.pdf?dl=0 |
10:20 | W06.2.7 | OptiShare: a Dynamic Channel Sharing Scheme for Power Efficient On-Chip Optical Architectures Eldhose Peter and Smruti R Sarangi, Indian Institute of Technology, IN Paper: https://www.dropbox.com/s/twokkhg0fv64ntu/OPTICS_2016_paper_9_PS3CR.pdf?... |
10:25 | W06.2.8 | Synthesis of Optical Circuits with Contradictory Optimization Objectives Arighna Deb1, Robert Wille2, Oliver Keszöcze1, Stefan Hillmich1 and Rolf Drechsler3 1University of Bremen, DE; 2JKU, Au; 3University of Bremen/DFKI GmbH, DE |
10:30 | W06.3 | Coffee Break and Poster Session |
11:00 | W06.4 | Morning Session II: Bringing Optical Communication into the Chip Chair: |
11:00 | W06.4.1 | Optical Interconnections and Power Consumption in Cloud Computing Alan Mickelson, University of Colorado at Boulder, US Abstract: https://www.dropbox.com/s/kwlkyrogyf85s8n/OPTICS_2016_paper_6_Alan_Micke... |
11:20 | W06.4.2 | Communication Requirements Inside a Chip Josè Flich, Universidad Politecnica de Valencia, ES Abstract: https://www.dropbox.com/s/tyejzrsvzqbyt3b/OPTICS_2016_paper_18_Jose_Flit... |
11:40 | W06.4.3 | Modeling and Analysis of Off-Chip Optical and Electrical Interconnects and Interfaces Jiang Xu, Hong Kong University of Science and Technology, HK Abstract: https://www.dropbox.com/s/iqbd43d77bq8wjk/OPTICS_2016_paper_17_Jiang_Xu.... |
12:00 | W06.5 | Lunch Break and Poster Session |
13:00 | W06.6 | Afternoon Session I: Silicon Photonic Interconnect Management Chair: |
13:00 | W06.6.1 | Impact of High-Speed Modulation on the Scalability of Silicon Photonic Sebastien Rumley, University of Columbia, US Abstract: https://www.dropbox.com/s/qbjmiuklfwessdj/OPTICS_2016_paper_10_Keren_Ber... |
13:30 | W06.6.2 | Towards Energy-Proportional Optical Interconnects Nikos Hardavellas, Northwestern University, US Abstract: https://www.dropbox.com/s/uj8elr2c7xyio9g/OPTICS_2016_paper_16_Nikos_Har... |
13:50 | W06.6.3 | Design Space Exploration of Optical Interfaces for Silicon Photonic Interconnects Olivier Sentieys, INRIA - University of Rennes 1, FR Abstract: https://www.dropbox.com/s/to2jjhr4azvt4xe/OPTICS_2016_paper_2_Olivier_Se... |
14:10 | W06.6.4 | Thermal Management of Manycore Systems with Photonic NoCs Ayse Coskun, Boston University, US Abstract: https://www.dropbox.com/s/qc2kg4ga1zjxb30/OPTICS_2016_paper_14_Ayse_Cosk... |
14:30 | W06.7 | Coffee Break and Poster Session |
15:00 | W06.8 | Afternoon Session II: Design Methods and Challenges Chair: |
15:00 | W06.8.1 | Network-on-Chip Using Silicon Photonics Waveguide Arrays Isabella Cerutti, Scuola Superiore Sant'Anna, IT Abstract: https://www.dropbox.com/s/z5zgn7mn2m6n0dv/OPTICS_2016_paper_8_Philippe_V... |
15:20 | W06.8.2 | Enabling Silicon Photonics Technology with EDA Ruping Cao, Mentor Graphics Corp. / Lyon Institute of Nanotechnologies, FR Abstract: https://www.dropbox.com/s/28olz0wdtb8d1hh/OPTICS_2016_paper_12_Ruping_Ca... |
15:40 | W06.8.3 | Fabrication Non-Uniformity in Silicon Photonic Interconnects Mahdi Nikdast, Polytechnique Montréal/McGill University, CA Abstract: https://www.dropbox.com/s/3mf9hm1ysgy4q84/OPTICS_2016_paper_20_Mahdi_Nik...
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16:00 | W06.8.4 | Layout Design of Wavelength-Routed Optical NoCs: the Global Picture Davide Bertozzi, University of Ferrara, IT Abstract: https://www.dropbox.com/s/ot5d3wrax3kgkfi/OPTICS_2016_paper_19_Davide_Be... |
16:20 | W06.8.5 | Thermal Aware Design Method for On-Chip Optical Interconnect Ian O'Connor, Lyon Institute of Nanotechnology, FR Abstract: https://www.dropbox.com/s/sg8xk25o1gon47i/OPTICS_2016_paper_20_Ian_Conno... |
16:40 | W06.9 | Panel Discussion Moderator: Panelists: |
Panelists: | ||
17:10 | W06.10 | Concluding Remarks and Closing Session Chair: Co-Chair: |