Date: Thursday 17 March 2016
Time: 11:00 - 12:30
Location / Room: Konferenz 6

Chair:
Davide Bertozzi, University of Ferrara, IT

Co-Chair:
Kees Goossens, Eindhoven University of Technology, NL

Reliable operation of NoCs is crucial for the correct operation of the complete system. Errors can occur at runtime coming from ill-defined clock domain crossing interfaces, partial design-time verification scenarios that did not cover all functional errors, and technology-scaling related sideffects that increase circuit's susceptibility to permanent and intermittent faults. The first paper addresses the implications of asynchronous clock domain crossing in virtual channel flow control. The second paper proposes a NoC architecture that enables the detection of functional bugs at runtime. The third paper employs dynamic link sharing for achieving fault tolerance 3D NoC designs.

Time	Label	Presentation Title Authors
11:00	10.2.1	CROSSOVER: CLOCK DOMAIN CROSSING UNDER VIRTUAL-CHANNEL FLOW CONTROL Speaker: Anastasios Psarras, Democritus University of Thrace, GR Authors: Michalis Paschou1, Anastasios Psarras1, Chrysostomos Nicopoulos2 and Giorgos Dimitrakopoulos1 1Democritus University of Thrace, GR; 2University of Cyprus, CY Abstract Technology scaling, process variations, and/or 3D integration make the design of fully synchronous Systems-on- Chip (SoC) a challenging task. Partitioning the SoC into Globally Asynchronous, Locally Synchronous (GALS) islands - aka clock domains - partially alleviates the difficulties in clock distribution. Such partitioning of the SoC is also necessary when supporting Dynamic Voltage and Frequency Scaling (DVFS) across parts of the system to minimize power consumption. The Network-on- Chip (NoC) is an inherently distributed architecture that is physically spread over the entire chip; thus, it should readily support communication across multiple asynchronous clock domains. In this paper, we generalize the fundamental properties of Virtual-Channel (VC) flow control across asynchronous clock domains. A new set of flow control rules is presented, which lead to efficient and deadlock-free communication, while still respecting the properties of traditional (synchronous) VC-based flow control. The derived flow control policy, called CrossOver, opens up a new design space, which is quantitatively explored in this paper. The goal of this investigation is to identify the configuration that maximizes throughput with the least cost, in terms of buffering requirements. Download Paper (PDF; Only available from the DATE venue WiFi)
11:30	10.2.2	CORRECT RUNTIME OPERATION FOR NOCS THROUGH ADAPTIVE REGION PROTECTION Speaker: Rawan Abdel-Khalek, University of Michigan, US Authors: Rawan Abdel-Khalek and Valeria Bertacco, University of Michigan, US Abstract Networks-on-chip (NoCs) are increasingly being adopted as the interconnect model for systems-on-chip and chip-multiprocessors. As the only communication medium in these designs, the NoC's functional correctness is critical. In practice, design-time verification of NoCs is always partial, due to their large scale and the challenges that hinder verification efforts. As a result, functional design bugs are bound to escape and potentially manifest at runtime, compromising system functionality. We propose REPAIR, a runtime solution to detect and recover from functional design errors that have escaped in NoCs. Existing runtime verification techniques incur significant area and performance overheads to monitor and check the correctness of every packet traversing the network. However, REPAIR relies on a retransmission-based technique that adaptively determines the subset of packets requiring protection by identifying dynamic network regions where the specific runtime execution is likely to expose functional design bugs. We achieve runtime correctness at lower performance and area costs, relative to a traditional solution: on average, we are able to achieve more than 50% better overall performance with 2-3x fewer retransmission buffers. Download Paper (PDF; Only available from the DATE venue WiFi)
12:00	10.2.3	FAULT-TOLERANT 3-D NETWORK-ON-CHIP DESIGN USING DYNAMIC LINK SHARING Speaker: Mehdi Modarressi, University of Tehran, IR Authors: Seyyed Hossein Seyyedaghaei Rezaei1, Mehdi Modarressi1, Reza Yazdani1 and Masoud Daneshtalab2 1University of Tehran, IR; 2KTH Royal Institute of Technology, SE Abstract The most important challenge in the emerging 3D integration technology is the higher temperature, particularly in the layers that are more distant from the heat sink, compared to planar 2D chips. High temperature, in turn, increases circuit's susceptibility to permanent and intermittent faults. On the other hand, the fast and high-bandwidth vertical links in the 3D integration technology have opened new horizons for network-on-chip (NoC) design innovations. In this paper, we leverage these ultra-low-latency vertical links to design a fault-tolerant 3D NoC architecture. In this architecture, permanent and intermittent defects on links and crossbars are bypassed by borrowing the idle bandwidth from vertically adjacent links and crossbars. Evaluation results under synthetic and realistic workloads show that the proposed fault-tolerance mechanism offers higher reliability and lower performance loss, when compared with state-of-the-art fault-tolerant 3D NoC designs. Download Paper (PDF; Only available from the DATE venue WiFi)
12:30	IP5-1, 288	RELIABILITY AND PERFORMANCE TRADE-OFFS FOR 3D NOC-ENABLED MULTICORE CHIPS Speaker: Partha Pande, Washington State University, US Authors: Sourav Das1, Janardhan Rao Doppa1, Partha Pande1 and Krishnendu Chakrabarty2 1Washington State University, US; 2Duke University, US Abstract Three-dimensional (3D) integration, a breakthrough technology to achieve "More Moore and More Than Moore," provides the benefits of better performance, lower power consumption, and increased bandwidth through the use of vertical interconnects and 3D stacking. The vertical interconnects enable the design of a high-bandwidth and energy-efficient small-world (SW) network-based 3D network-on-Chip (3D SWNoC) for massive multicore platforms. However, the anticipated performance gain of a 3D SWNoC-enabled multicore chip may be compromised due to the potential failures of through-silicon- vias (TSVs) that are predominantly used as vertical interconnects. In particular, due to the non-homogeneous traffic patterns, heavily used TSVs may wear-out quickly and can also contribute to the wear-out of neighboring TSVs. As a result, the mean-time-to-failure (MTTF) of those TSVs will decrease, which will adversely affect the overall lifetime of the chip. In this paper, we address this traffic-dependent TSV wear-out problem in 3D SWNoC. We demonstrate that by employing an adaptive routing mechanism, we can improve the MTTF of 3D SWNoC significantly while still providing 21% lower energy-delay-product (EDP) compared to a conventional 3D MESH. Download Paper (PDF; Only available from the DATE venue WiFi)
12:31	IP5-2, 455	MEMORY-ACCESS AWARE DVFS FOR NETWORK-ON-CHIP IN CMPS Speaker: Yuan Yao, KTH Royal Institute of Technology, SE Authors: Yuan Yao and Zhonghai Lu, KTH Royal Institute of Technology, SE Abstract We present a new DVFS technique for network-on-chip (NoC) that adjusts the voltage/frequency scales of routers according to memory-access characteristics of application running on the CMP. The memory characteristics are periodically profiled, reflecting both resource-access density in the network and memory-access criticality for application performance. The network conducts per-router voltage/frequency tuning using the memory-access density information while it performs priority-based switch allocation to speed up critical packets and avoid starvation using the memory-criticality information. Compared to a latest per-router DVFS approach, benchmark experiments demonstrate that our memory-access characteristics aware DVFS technique achieves not only better power saving, energy-delay product, but also enhanced network and application performance. Download Paper (PDF; Only available from the DATE venue WiFi)
12:30		End of session Lunch Break in Großer Saal + Saal 1 Keynote Lecture in "Saal 2" 13:30 - 14:00