Date: Tuesday 10 March 2015
Time: 17:00 - 18:30
Location / Room: Les Bans
Chair:
Vikas Chandra, ARM, US
Co-Chair:
Mehdi Tahoori, Karlsruhe Institute of Technology, DE
Many new technologies are being proposed as alternatives to conventional CMOS design. Resiliency, including robustness, reliability and fault modeling, will be a key factor in their success. This session includes results on several of these, as well as IP presentations on two others.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 17:00 | 4.7.1 | (Best Paper Award Candidate) DIGITAL CIRCUITS RELIABILITY WITH IN-SITU MONITORS IN 28NM FULLY DEPLETED SOI Speakers: Marine Saliva1, Florian Cacho1, Vincent Huard1, Xavier Federspiel1, Damien Angot1, Ahmed Benhassain1, Alain Bravaix2 and Lorena Anghel3 1STMicroelectronics, FR; 2IM2NP-ISEN, FR; 3TIMA, FR Abstract Aging induced degradation mechanisms occurring in digital circuits are of a greater importance in the latest technologies. Monotonous degradation such as Bias Temperature Instability (BTI) or Hot Carrier Injection (HCI) but also sudden degradation such as Dielectric Breakdown (DB) are identified as the major sources of reliability hazard. The impact of these phenomena on the digital circuits is usually observed in terms of timing degradations and thus it may result in setup/hold violation. In this paper we will focus on the impact of aging related degradation mechanisms on timing. In-situ monitor is a promising strategy to measure timing slacks and to provide pre-error warning prior timing violation. A dedicated structure has been developed to measure and benchmark the behaviors of different monitors. The technology used for the test structure and in-situ monitors are processed in 28nm Fully Depleted SOI. The designs of monitors are mostly based on delay elements. Three types of delays are proposed in this paper: flip-flop's Master delay, Buffers delay and Passive delay. In addition, we investigate the impact of global and local variations on the accuracy of the measurements by providing complete monitors characterization. Experimental results show a good agreement with SPICE simulation. Finally the proposed in-situ monitors will be compared and their applications to circuit aging prediction will be discussed. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 17:30 | 4.7.2 | READ/WRITE ROBUSTNESS ESTIMATION METRICS FOR SPIN TRANSFER TORQUE (STT) MRAM CELL Speakers: Elena Ioana Vatajelu1, Rosa Rodriguez-Montañés2, Marco Indaco1, Michel Renovell3, Paolo Prinetto1 and Joan Figueras2 1Politecnico di Torino, IT; 2Universitat Politecnica de Catalunya, ES; 3LIRMM-CNRS, Abstract — The rapid development of low power, high density, high performance SoCs has pushed the embedded memories to their limits and opened the field to the development of emerging memory technologies. The Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) has emerged as a promising choice for embedded memories due to its reduced read/write latency and high CMOS integration capability. Under today aggressive technology scaling requirements, the STT-MRAM is affected by process variability making robustness evaluation an important concern. In this paper, we provide new metrics for robustness prediction of an STT-MRAM memory cell. Independent Robustness Margin metrics are defined for Read Operation and Write Operation based on the electrical characteristics of the memory cell and the fabrication induced variability. These metrics are used to estimate the extreme parameter variation causing the cell failure, Current Noise Margins and the Failure Probability of the STT-MRAM cell. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 18:00 | 4.7.3 | FAULT MODELING IN CONTROLLABLE POLARITY SILICON NANOWIRE CIRCUITS Speakers: Hassan Ghasemzadeh Mohammadi1, Pierre-Emmanuel Gaillardon2 and Giovanni De Micheli1 1École Polytechnique Fédérale de Lausanne (EPFL), CH; 2École Polytechnique Fédérale de Lausanne (EPFL), Abstract Controllable polarity silicon nanowire transistors are among the promising candidates to replace current CMOS in the near future owing to their superior electrostatic characteristics and advanced functionalities. From a circuit testing point of view, it is unclear if the current CMOS and FinFET fault models are comprehensive enough to model all defects of controllable polarity nanowires. In this paper, we deal with the above problem using inductive fault analysis on three-independent-gate silicon nanowire FETs. Simulations revealed that the current fault models, i.e. stuck-open faults, are insufficient to cover all modes of operation. The newly introduced test algorithm for stuck open can adequately capture the malfunction behavior of controllable polarity logic gates in the presence of nanowire break and bridge on polarity terminals. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 18:30 | IP2-3, 849 | RETRAINING BASED TIMING ERROR MITIGATION FOR HARDWARE NEURAL NETWORKS Speakers: Jiachao Deng1, Yuntan Fang1, Zidong Du1, Ying Wang1, Huawei Li1, Olivier Temam2, Paolo Ienne3, David Novo3, Xiaowei Li1, Yunji Chen1 and Chengyong Wu1 1State Key Laboratory of Computer Architecture, ICT, CAS, Beijing, China †University of Chinese Academy of Sciences, Beijing, China, CN; 2INRIA Saclay, France, FR; 3École Polytechnique Fédérale de Lausanne (EPFL), CH Abstract Recently, neural network (NN) accelerators are gaining popularity as part of future heterogeneous multi-core architectures due to their broad application scope and excellent energy efficiency. Additionally, since neural networks can be retrained, they are inherently resillient to errors and noises. Prior work has utilized the error tolerance feature to design approximate neural network circuits or tolerate logical faults. However, besides high-level faults or noises, timing errors induced by delay faults, process variations, aging, etc. are dominating the reliability of NN accelerator under nanoscale manufacturing process. In this paper, we leverage the error resiliency of neural network to mitigate timing errors in NN accelerators. Specifically, when timing errors significantly affect the output results, we propose to retrain the accelerators to update their weights, thus circumventing critical timing errors. Experimental results show that timing errors in NN accelerators can be well tamed for different applications. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 18:31 | IP2-4, 269 | DICTIONARY-BASED SPARSE REPRESENTATION FOR RESOLUTION IMPROVEMENT IN LASER VOLTAGE IMAGING OF CMOS INTEGRATED CIRCUITS Speakers: Tenzile Berkin Cilingiroglu, Mahmoud Zangeneh, Aydan Uyar, W. Clem Karl, Janusz Konrad, Ajay Joshi, Bennett B. Goldberg and M. Selim Unlu, Boston University, US Abstract The rapid decrease in the dimensions of integrated circuits with a simultaneous increase in component density have introduced resolution challenges for optical failure analysis tech- niques. Although optical microscopy efforts continue to increase resolution of optical systems through hardware modifications, signal processing methods are essential to complement these efforts to meet the resolution requirements for the nanoscale integrated circuit technologies. In this work, we focus on laser voltage imaging as the optical failure analysis technique and show how an overcomplete dictionary-based sparse representation can improve resolution and localization accuracy. We describe a reconstruction approach based on this sparse representation and validate its performance on simulated data. We achieve an 80% reduction of the localization error. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 18:30 | End of session | |