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W5 3D Integration - Applications, Technology, Architechture, Design, Automation, and Test

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Topic Areas

You are invited to participate and submit your contributions to the DATE 2012 Friday Workshop on 3D Integration. The areas of interest include (but are not limited to) the following topics:

  • 3D technologies: chip-on-chip, micro-bumping, contactless, and through-silicon-vias interconnect
  • TSV formation, perm./temp. wafer (de-)bonding
  • 3D architectures and design space exploration
  • 3D combinations of logic, memory, analog, RF
  • Application, product, or test chip case studies
  • 3D design methods and EDA tools
  • Signal and power integrity, and ESD in 3D
  • Thermo(-mechanical) analysis and -aware design
  • Chip-package co-design for 3D
  • Test, design-for-test, and debug techniques for 3D
  • Wafer test access, KGD test, thin-wafer handling
  • Economic benefit/cost trade-off studies
  • Standardization initiatives

Submission Instructions

Submissions are invited in the form of (extended) abstracts not exceeding two pages and must be sent in as PDF file to <qxuatcse [dot] cuhk [dot] edu [dot] hk> and <sskatecs [dot] soton [dot] ac [dot] uk> with "DATE12-3D-WS" as subject. All submissions will be evaluated for selection with respect to their suitability for the workshop, originality, and technical soundness. Selected submissions can be accepted for regular or poster presentation. At the workshop, an Electronic Workshop Digest will be made available to all workshop participants, which will include all material that authors are willing to provide: abstract, paper, slides, poster, etc.

Paper Submission deadlineDecember 11, 2011
Notification of AcceptanceDecember 19, 2011
Camera-Ready Material due dateFebruary 25, 2012
Groups:
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