SPEAKERS' BIOGRAPHIES

Prof. Yu (Kevin) Cao received the B.S. degree in physics from Peking University in 1996. He received the M.A. degree in biophysics and the Ph.D. degree in electrical engineering from University of California, Berkeley, in 1999 and 2002, respectively. He joined Arizona State University in 2004 where he is now Associate Professor of Electrical Engineering. He has published more than 140 articles and coauthored one book. His research interests include physical modeling of nanoscale technologies, design solutions for variability and reliability, and reliable integration of post-silicon technologies. Dr. Cao received the 2009 ACM SIGDA Outstanding New Faculty Award, 2007 Best Paper Award at ISLPED, the 2006 NSF CAREER Award, the 2006 and 2007 IBM Faculty Award, the 2004 Best Paper Award at ISQED, and the 2000 Beatrice Winner Award at ISSCC. He has served on numerous technical program committees and is a member of the IEEE EDS Compact Modeling Technical Committee.

Georges G.E. Gielen received the MSc and PhD degrees in Electrical Engineering from the Katholieke Universiteit Leuven, Belgium, in 1986 and 1990, respectively. From 1986 to 1990, he was appointed as a research assistant by the Belgian National Fund of Scientific Research for carrying out his Ph.D. research in the ESAT-MICAS laboratory of the Katholieke Universiteit Leuven. In 1990, he was appointed as a postdoctoral research assistant and visiting lecturer at the department of Electrical Engineering and Computer Science of the University of California, Berkeley. From 1991 to 1993, he was a postdoctoral research assistant of the Belgian National Fund of Scientific Research at the ESAT-MICAS laboratory of the Katholieke Universiteit Leuven. In 1993, he was appointed as a tenure research associate of the Belgian National Fund of Scientific Research and at the same time as an assistant professor at the Katholieke Universiteit Leuven. In 1995 he promoted to associate professor at the same university. His research interests are in the design of analog and mixed-signal integrated circuits, and especially in analog and mixed-signal CAD tools and design automation (modeling, simulation and symbolic analysis, analog synthesis, analog layout generation, analog and mixed-signal testing). He is coordinator or partner of several (industrial) research projects in this area. He has authored or coauthored one book and more than 100 papers in edited books, international journals and conference proceedings. He regularly is a member of the Program Committees of international conferences (ICCAD, ED&TC...), he has served as Associate Editor of the IEEE Transactions on Circuits and Systems, part I, and is a member of the Editorial Board of the Kluwer international journal on Analog Integrated Circuits and Signal Processing. He is a member of IEEE and ACM.

Prof. Subhasish Mitra leads the Robust Systems Group in the Department of Electrical Engineering and the Department of Computer Science of Stanford University. Before joining Stanford, he was a Principal Engineer at Intel Corporation. Prof. Mitra’s research interests include robust system design, VLSI design, CAD, validation and test, and emerging nanotechnologies. His X-Compact technique for test compression has been used in more than 50 Intel products, and has influenced major CAD tools.  The IFRA technology for post-silicon validation, created jointly with his student, was characterized as “a breakthrough” in the Communications of the ACM. His work on the first demonstration of imperfection-immune carbon nanotube VLSI circuits, jointly with his students and collaborators, was selected by NSF as a Research Highlight to the US Congress, and was highlighted as “a significant breakthrough” by the Semiconductor Research Corporation and the MIT Technology Review. Prof. Mitra's major honors include the Presidential Early Career Award for Scientists and Engineers, the highest honor bestowed by the United States on early-career outstanding scientists and engineers, NSF CAREER Award, Terman Fellowship, IEEE CAS/CEDA Donald O. Pederson Award for the best paper published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ACM SIGDA Outstanding New Faculty Award, Best Paper Award at the IEEE/ACM Design Automation Conference, IBM Faculty Awards, Intel Divisional Recognition Award “for a Breakthrough Soft Error Protection Technology,” Best Paper Award at the Intel Design and Test Technology Conference, and the Intel Achievement Award, Intel’s highest corporate honor, “for the development and deployment of a breakthrough test compression technology.”  Prof. Mitra also serves as an invited member on DARPA’s Information Science and Technology Study Group.

Dr. Sani Nassif received his PhD from Carnegie-Mellon University in the eighties. He worked for ten years at Bell Laboratories on various aspects of design and technology coupling including device modeling, parameter extraction, worst case analysis, design optimization and circuit simulation. He joined the IBM Austin Research Laboratory in January 1996 where he is presently managing the Silicon Analytics Department, which is focused on design/technology coupling and includes activities in: model to hardware matching, simulation and modeling, statistical modeling, statistical technology characterization and related areas. Sani is a fellow of the IEEE, a member of the IBM Academy of Technology, and holds 44 US and international patents.