SPEAKERS' BIOGRAPHIES

Reinig Helmut is a principal design engineer in the Intellectual Property Reuse department within Infineon's Enabling Technologies and Services group. He received both a diploma degree and a Ph.D. degree in computer science and information technology from Kaiserslautern University of Technology, Germany.  Dr. Reinig has industry experience for more than 15 years, first in Siemens Semiconductor Division, then at Infineon Technologies AG, with different areas of responsibility. During the last five years he works on concept and design of communication backbone infrastructures for heterogeneous multiprocessor platforms. A special focus is being put to communication backbones for mobile devices with strict power consumption and package size budgets. His research interests include modern SoC design as well as electronic-system-level performance simulations.

Luca Carloni is an Associate Professor of Computer Science at Columbia University in the City of New York. He holds a Laurea Degree Summa cum Laude in Electrical Engineering from the University of Bologna, Italy, a Master of Science in Engineering from the University of California at Berkeley, and a Ph.D. in Electrical Engineering and Computer Sciences from the University of California at Berkeley.  Luca received the "Faculty Early Career Development (CAREER) Award" from the National Science Foundation in 2006, was selected as an Alfred P. Sloan Research Fellow in 2008, and received the Young Investigator Award from the Office of Naval Research in 2010. At Berkeley Luca was the 2002 recipient of the Demetri Angelakos Memorial Achievement Award in recognition of altruistic attitude towards fellow graduate students. In 2002, one of his papers was selected for "The Best of ICCAD," a collection of the best IEEE International Conference on Computer-Aided Design papers of the past 20 years.  His research interests include design tools and methodologies for multicore system-on-chip platforms with emphasis on system-level design and communication synthesis, design and optimization of networks-on-chip, and distributed embedded systems design. Luca coauthored over sixty-five refereed papers and is the holder of one patent.  Luca is an associate editor of the ACM Transactions in Embedded Computing Systems. He has served in the technical program committee of several conferences including DAC, DATE, ICCAD, and EMSOFT. He has been the tutorial chair of the Embedded Systems Week in 2008 and 2009 and is the program chair of the 2010 International Conference on Embedded Software (EMSOFT) and the 2010 International Symposium on Networks-on-Chip (NOCS).

Raj Yavatkar is an Intel Fellow and director of the System-on-Chip (SoC) Architecture for the Intel Architecture Group at Intel Corporation. He leads the development of modular design and validation technologies to enable high-integration SoC products with a quick turn-around time. Dr. Yavatkar has held several positions at Intel including leading platform validation architecture for Intel's CPU and chipset products. He led the formation of the Systems Technology Lab involved in advanced R&D in the areas of system architecture and platform technologies. From 1999 through 2004, he was the Chief Software Architect for Intel's IXP family of network processors.

Michael Dimelow is a director of marketing for ARM Processor Division. He is responsible for defining and executing the CoreLink™ interconnect, memory controller and CoreSight™ debug and trace product strategy, and the commercial direction and go-to-market plans for the ARM compute sub-system roadmap. Michael has over 20 years experience operating at the heart of the communications industry, having worked for Nokia, Ericsson, Mercury One2One, Your Communications and TTPCom before moving to ARM in 2006. During this time he has held a variety of business management, marketing and engineering roles that have led to the successful commercial roll-out of products within mobile and internet service providers, network infrastructure and consumer device product manufacturers. Michael holds an MSc in Electronic Engineering from The University of Surrey and an MBA from Manchester Business School.

Philippe D’Audigier is SoC hardware design manager for the Home Video Division of STMicroelectronics. He is responsible for SoC hardware architecture definition, including NoC, SoC RTL development, and functional and performance verification of Set-Top-Box SoCs.