W5 3D Integration - Applications, Technology, Architecture, Design, Automation, and Test

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Date: Friday 16 March 2012
Time: 08:30 - 16:40
Location / Room: Saal 5

Sandeep K. Goel, TSMC,
Qiang Xu, The Chinese University of Hong Kong,
Saqib Khursheed, University of Southampton,

The proceedings may be downloaded from one of the following two links:

The file "Informal Proceedings.pdf" has an index with links to all the submitted papers and presentations, that were a part of the 3D WS program.

3D Integration is a promising technology for extending Moore's momentum in the next decennium, offering heterogeneous technology integration, higher transistor density, faster interconnects, and potentially lower cost and time-to-market. But in order to produce 3D chips, new capabilities are needed: process technology, architectures, design methods and tools, and manufacturing test solutions. The goal of this Workshop is to bring together researchers, practitioners, and others interested in this exciting and rapidly evolving field, in order to update each other on the latest state-of-the-art, exchange ideas, and discuss future challenges.

The last three editions of this workshop took place in conjunction with:

The workshop program contains the following elements.

  • One invited keynote address
  • Two invited talks
  • Two sessions with in total twelve regular presentations
  • Two poster sessions
  • One panel session
Moderator: Stephan Eggersglüß - German Research Center for Artificial Intelligence, DE
0830Welcome Address
0840Keynote Address: Design of 3D Specific Systems: Prospectives and Interface Requirements
Paul Franzon - North Carolina State University, US

Abstract: After years of research and development, Through-Silicon Vias (TSVs) are becoming a manufacturing reality. Soon, a wave a new TSV-based 3D stacked ICs (and "2½D"-stacked ICs) will hit the market, including CMOS image sensors, memory cubes, stacked FPGAs, and memory-on-logic. This will be followed by a set of more sophisticated products likely to have a focus on heterogeneous integration. For digital systems, one particularly benefit for going into the third dimension is reduced power consumption. However, to justify the investment it must be possible to achieve power savings of 25% or more. This cannot be achieved solely through shorter wires! 3D-specific design solutions are needed.

A particular complexity in 3D integration is that designs that might be assembled into a 3D stack are likely to be designed at different times and places. This creates the need for common interface IP and interchange standards. The requirements and progress towards these will be presented and discussed.
0925Invited Talk: 3D IC Test Challenges and Emerging Solutions
Steve Pateras - Mentor Graphics, US

Abstract: 3D IC offers a compelling alternative to traditional scaling for achieving advances in performance, reduced power consumption, cost reduction, and increased functionality in a small package. Unfortunately 3D IC packaging also creates some new challenges for manufacturing test. Wafer sort will need to deliver higher test quality to ensure acceptable final package yields and thus limit the cost impact of stacking bad die in a 3D package. Stacked die also create significant test access problems since the die-level I/O may not be accessible from within the package. Ensuring that all inter-die TSV connections are adequately tested further complicates the overall test problem. This presentation will review test solutions available to cost-effectively test 3D ICs from wafer sort to packaged assembly.
Posters (see list bellow) - coffee + tea break
1030SESSION 3: Design, Automation and Test of 3D-ICs
Moderator: Andreas Hansson - ARM, UK
1030Fabrication Cost Analysis for 2D, 2.5D, and 3D IC Design
Chao Zhang, Guangyu Sun - Peking U, CN
1045Performance and Efficiency of 3D Stacked DRAM in a Multicore System
Sachin Idgunji - ARM, US
Djordje Jevdjic - EFPL, CH
Dragomir Milojevic - IMEC, BE
Emre Ozer - ARM, US
1100 Designing a 3D Stacked Vector Cache
Ryusuke Egawa - Tohoku U/JST CREST, JP
Yusuke Endo - Tohoku U, JP
Jubei Tada - Yamagata U, JP
Hiroyuki Takizawa, Hiroaki Kobayashi - Tohoku U/JST CREST, JP
Gensuke Goto - Yamagata U, JP
1115Quality Inspection Strategy in 3D-Chip Formation Process
Wolfram Steller, Stephan Dobritz, Juliane Krause - Fraunhofer IZM - ASSID, DE
1130TSV Cost Aware Circuit Partitioning for 3D-SOCs
Amit Kumar, Sudhakar Reddy - U of Iowa, US
Irith Pomeranz - Purdue U, US
Bernd Becker - Albert-Ludwigs-U, DE
1145Dynamic Thermal Optimization for 3D NOC
Ra'ed Al-Dujaily, Terrence Mak, Fei Xia, Alex Yakovlev - Newcastle U, UK
Kai-Pui Lam, The Chinese U of Hong Kong, HK
Chi-Sang Poon, Massachusetts Institute of Technology, US
1300SESSION 4: Efficient 3D System-in-Package: Reliability, Failure Analysis and Test (ESiP)
Moderator: U. Ingelsson, EIS by Semcon AB, SE
1300System-in-Package: Need for a Coherent Chip-Package-Board View
Klaus Pressel - Infineon, DE
1315Adapting WLP technologies for packaging of MEMS-SiP
Heikki Kuisma and Sami Nurmi - VTI, FI
1330Failure analysis of open TSV interconnects
Frank Altmann - Fraunhofer Institute for Mechanics of Materials IWM, DE
Franz Schrank - austriamicrosystems AG, AT
1345Defect analysis in wafer bonded interfaces for 3D integration
Matthias Petzold - Fraunhofer Institute for Mechanics of Materials IWM, DE
Cathal Cassidy - austriamicrosystems AG, AT
1400Aspects of probing fine pitch structures in 3D using dedicated probe tools
Thomas Thaerigen - Cascade Microtech, DE
Peter Hanaway - Cascade Microtech, US
Stojan Kanev - Cascade Microtech, DE
Erik Jan Marinissen - IMEC, BE
1415Contact-less testing platform based on capacitive coupling: I/O pad and probe-card design considerations
Roberto Canegallo - ST Microelectronics, IT
Eleonora Franchi - U of Bologna, IT
Cristian Gozzi - Technoprobe, IT
Andrea Santomartino - SPEA, IT
Posters (see list bellow) - coffee + tea break
Moderator: Bjørn B. Larsen - The Norwegian University of Science and Technology, NO
"Design, Implementation, and Test of 3D-MAPS - a Many-Core Processor Using 3-D Integration Technology"
Hsien-Hsin S. Lee - Georgia Tech., US
"Chip package and board co-design challenges and solution for 3D ICs"
Moderator: Jochen Reisinger - Infineon, AT
Peter Schneider - Fraunhofer IIS - EAS, DE
Rainer Kress - Infineon, DE
Heiko Dudek - Cadence, US
Franz Schrank - austriamicrosystems, AT
Ridha Hamza - DOCEA Power, FR


1000-1030h and 1430-1500h

  1. Timing-aware and Efficient TSV Grouping for 3D-ICs
    Yi Zhao, Saqib Khursheed, Bashir M. Al-Hashimi - Univ of Southampton, UK
  2. Cell-Based Die-to-Die Wire-Independent Clock Synchronization,
    Ji-Wei Ke, Shi Yu Huang, Chao-Wen Tzeng - National Tsing Hua Univ, TW
    Yung-Fa Chou, Ding-Ming Kwai - Industrial Tech Research Inst, TW
  3. A 3D Stacked Multi-Core Processor Platform with Improved Testability
    Paolo Giovannini, Giulia Beanato, Alessandro Cevrero, Panagiotis Athanasopoulos, Yusuf Leblebici - EFPL, CH
  4. An Approach for Thermal Optimization of 3D-IC and package
    Andy Heinig, Christoph Sohrmann, Uwe Knöchel - Fraunhofer Inst for Integrated Circuits, DE
  5. Exact Wafer Matching Process for 3D Wafer-to-Wafer Integration
    G. Di Natale, M. L. Flottes, R. Giroudeau, F. Hernandez - LIRMM, FR
  6. A Novel Inductive Coupling Communications Based on Through Silicon Via Technology
    Khaled Salah, Alaa El Rouby - Mentor Graphics, EG
    Hani Ragai - Ain-Shams Univ, EG
    Yehea Ismail - AUC Univ, EG
  7. The Impact of EDA Tools in 3D IC Design Space Exploration: A Case Study
    Abir M'zah, Omar Hammami - ENSTA ParisTech, FR
    Jouhar Mouine - ENIT, TN
  8. Logic Layer Communication Platform for 3D-Stacked Memory-on-Processor Architectures
    Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila - Univ of Turku, FI
  9. Yield Driven System Integration for 2.5D SoC
    Li Jiang, Qiang Xu - The Chinese Univ. of Hong Kong, HK
    Bill Eklow - Cisco Systems, US
  10. A TSV-Defect-Tolerance Test Interface for 3D ICs
    Che-Wei Chou, Jin-Fu Li - National Central Univ, TW
  11. A Built-in Delay Measurement Method for TSVs
    Han-Yu Wu, Che-Wei Chou, Jin-Fu Li - National Central Univ, TW
  12. TSV-Safe: An Architectural Level Framework to Mitigate TSV Electromigration for 3D ICs
    Yuanqing Cheng, Lei Zhang, Yinhe Han, Xiaowei Li - Chinese Academy of Sciences, CN