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FROM RESEARCH TO MARKET Biography: Laurent Malier heads the LETI - Laboratory for Electronics and Information Technology -, a research institute, based in France, within Minatec Innovation Campus. Laurent Malier graduated from Ecole Polytechnique and received his PhD degree in Solid State Physics in 1994. In 1996, he joined the French ministry of Defence, in charge of R&D strategy and programs in electronics, where he chaired the European cooperation of MODs in electronic components. In 2001, he joined Alcatel Optronics, a company producing optoelectronic components for optical telecommunications, in charge of new product developments. He took over the semiconductor business unit of Alcatel Optronics, which became Avanex in 2003. Laurent Malier joined the LETI in 2004, first as VP strategy and programs. |
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SUCCESSFUL R&D COLLABORATIONS AS A COMPETITIVE ADVANTAGE Abstract: STs Grenoble center was born as a spin-off from a Grenoble research lab several decades ago. Since then we have continued to maintain our innovation leadership with long-term Public-Private Partnerships in Grenoble, France and Europe. Starting in 1992, ST has partnered with its competitors to build its 200mm and 300 mm R&D centers and fabs in Crolles, near Grenoble. In 2008, ST joined ISDA alliance in Fishkill NY to collaborate to its 32/28nm and 20nm CMOS processes. More recently, ST has reinforced and enlarged the scope of its local R&D partnership to Design and Design Automation. This complete eco-system is now bringing valuable innovation to our products and our customers. Biography: From 1985 to 1989, Magarshack designed microprocessors arithmetic blocks at AT&T Bell Labs in New Jersey, Pennsylvania and California. In 1989, he joined Thomson-CSF in Grenoble, France, as libraries and ASIC Manager. In 1994, Magarshack joined the Central R&D of SGS-THOMSON Microelectronics (now STMicroelectronics), where he held several Program Management roles in advanced CMOS Design Platforms. Since 2005, Magarshack heads ST’s Central Library, IP and CAD organisation, which defines and provides design solutions to all ST Product Groups in CMOS, embedded NVM and BCD processes, ranging from 0.35um to 20nm technologies. |
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INVESTING IN THE TOP TALENT FOR EDA Abstract: Mentor Graphics has a long track record of investing in Europe for R&D expertise. Over the last year, despite the economic conditions, we have continued to recruit in France, the UK and Poland. Our industry is a meritocracy which relies on the hiring, nurturing and retention of the best world-class engineers available in electronics and associated fields. This presentation will outline why we invest in Europe, why France is such a significant part of this and look at the particular place Grenoble has in this story. |
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