2.2 System-Level Techniques to Handle Performance, Reliability and Thermal Issues
| 1130 | VESPA: VARIABILITY EMULATION FOR SYSTEM-ON-CHIP PERFORMANCE ANALYSIS V Kozhikkottu, R Venkatesan and A Raghunathan, Purdue U, US |
| 1200 | THERMAL-AWARENESS ON-LINE TASK ALLOCATION FOR 3D MULTI-CORE PROCESSOR THROUGHPUT OPTIMIZATION C L Lung, National Tsing-Hua U & ITRI, Taiwan, ROC Y L Ho and S C Chang, National Tsing-Hua U, ROC D M Kwai, ITRI, ROC |
| 1230 | ENDURANCE-ENHANCED FLASH TRANSLATION LAYER FOR NAND FLASH MEMORY THROUGH REUSE STRATEGY Y Wang, D Liu, Z Qin and Z Shao, The Hong Kong Polytechnic U, PRC |
| 1245 | REGISTER ALLOCATION FOR SIMULTANEOUS REDUCTION OF ENERGY AND PEAK TEMPERATURE ON REGISTERS T Liu, M Li and C J Xue, City U of Hong Kong, PRC |
| IPs | IP1-1, IP1-8, IP1-9 |
| 1300 | LUNCH BREAK |
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