DATE 2011

D12 Logic and Technology Dependent Synthesis for Deep-Submicron Circuits

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Combinational and sequential synthesis; data structures for synthesis; technology mapping; hierarchical and non-hierarchical controller synthesis; state assignment; methods for FSM optimization, synthesis and analysis; asynchronous and mixed synchronous/asynchronous circuits; performance and timing driven synthesis; PLD and FPGA synthesis; combined logic synthesis and layout design, statistical timing analysis, timing closure; arithmetic circuits
 

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