DATE 2010

D17 Interconnect, EMC, ESD and Packaging Modelling

Modeling, characterization and analysis of on and off chip interconnects and packaging. Coupling effects and guided waves on interconnects. Modeling and analysis of noise due to electromagnetic interaction on signal, power/ground and substrate. Specific topics are model order reduction for interconnects and passive systems; electrostatic discharge (ESD); macromodels for variability-aware timing analysis; 3D interconnects (or interconnect models for 3D chips); interconnect parameter extraction and circuit model generation; signal integrity analysis; power and ground network analysis; thermal modeling and analysis; modeling for manufacturability, reliability, and robustness; electromagnetic emission, susceptibility and compatibility; electrical overstress
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