NTX: An Energy-efficient Streaming Accelerator for Floating-point Generalized Reduction Workloads in 22 nm FD-SOI
Fabian Schuiki1,a, Michael Schaffner1,b and Luca Benini2
1IIS, ETH Zürich Zürich, Switzerland
afschuiki@iis.ee.ethz.ch
bschaffner@iis.ee.ethz.ch
2IIS, ETH Zürich Zürich, Switzerland DEI, University of Bologna Bologna, Italy
lbenini@iis.ee.ethz.ch
ABSTRACT
Specialized coprocessors for Multiply-Accumulate (MAC) intensive workloads such as Deep Learning are becoming widespread in SoC platforms, from GPUs to mobile SoCs. In this paper we revisit NTX (an efficient accelerator developed for training Deep Neural Networks at scale) as a generalized MAC and reduction streaming engine. The architecture consists of a set of 32 bit floating-point streaming co-processors that are loosely coupled to a RISC-V core in charge of orchestrating data movement and computation. Post-layout results of a recent silicon implementation in 22nm FD-SOI technology show the accelerator’s capability to deliver up to 20 Gflop/s at 1.25 GHz and 168mW. Based on these results we show that a version of NTX scaled down to 14nm can achieve a 3× energy efficiency improvement over contemporary GPUs at 10.4× less silicon area, and a compute performance of 1.4 Tflop/s for training large state-of-the-art networks with full floating-point precision. An extended evaluation of MAC-intensive kernels shows that NTX can consistently achieve up to 87% of its peak performance across general reduction workloads beyond machine learning. Its modular architecture enables deployment at different scales ranging from high-performance GPU-class to low-power embedded scenarios.
Keywords: Processor Architecture, Accelerator, Deep Learning, VLSI, Linear Algebra
