Review of Methodologies for Pre- and Post-Silicon Analog Verification in Mixed-Signal SOCs
Georges Gielen1, Nektar Xama1, Karthik Ganesan2 and Subhasish Mitra2
1Dept. Electrical Engineering, KU Leuven, Belgium
2Dept. Computer Science, Stanford University, California, USA
ABSTRACT
The integration of increasingly more complex and heterogeneous SOCs results in ever more complicated demands for the verification of the system and its underlying subsystems. Pre-silicon design validation as well as post-silicon test generation of the analog and mixed-signal (AMS) subsystems within SOCs proves extremely challenging as these subsystems do not share the formal description potential of their digital counterparts. Several methods have been developed to cope with this lack of formalization during AMS pre-silicon validation, including model checkers, affine arithmetic formalisms and equivalence checkers. However, contrary to the industrial practice for digital circuits of using formal verification and ATPG tools, common industry practice for analog circuits still largely defaults to simulation-based validation and test generation. A new formal digital-inspired technique, called AMS-QED, can potentially solve these issues in analog and mixed-signal verification.
