A Security Architecture for RISC-V based IoT Devices
Lukas Auer1,a, Christian Skubich2 and Matthias Hiller1,b
1Fraunhofer Institute for Applied and Integrated Security AISEC, Garching near Munich, Germany
aLukas.Auer@aisec.fraunhofer.de
bMatthias.Hiller@aisec.fraunhofer.de
2Fraunhofer Institute for Integrated Circuits IIS, Division Engineering of Adaptive Systems EAS, Dresden, Germany
Christian.Skubich@eas.iis.fraunhofer.de
ABSTRACT
New IoT applications are demanding for more and more performance in embedded devices while their deployment and operation poses strict power constraints. We present the security concept for a customizable Internet of Things (IoT) platform based on the RISC-V ISA and developed by several Fraunhofer Institutes. It integrates a range of peripherals with a scalable computing subsystem as a three dimensional Systemin-Package (3D-SiP).
The security features aim for a medium security level and target the requirements of the IoT market. Our security architecture extends given implementations to enable secure deployment, operation, and update. Core security features are secure boot, an authenticated watchdog timer, and key management.
The Universal Sensor Platform (USeP) SoC is developed for GLOBALFOUNDRIES’ 22FDX technology and aims to provide a platform for Small and Medium-sized Enterprises (SMEs) that typically do not have access to advanced microelectronics and integration know-how, and are therefore limited to Commercial Off-The-Shelf (COTS) products.
Keywords: RISC-V, Device security, Secure boot, Watchdog timer, IoT.
