Hidden-Delay-Fault Sensor for Test, Reliability and Security
Giorgio Di Natale, Elena Ioana Vatajelu, Kalpana Senthamarai Kannan and Lorena Anghel
Univ. Grenoble Alpes, CNRS, Grenoble INP, TIMA, Grenoble, France
ABSTRACT
In this paper we present a novel hidden-delay-fault sensor design and a preliminary analysis of its circuit integration and applicability. In our proposed method, the delay sensing is achieved by sampling data on both rising and falling clock edges and using a variable duty cycle to control the length of the path to be tested. The main advantage of our proposed method is that it works at nominal frequency, it can detect hidden-delay-faults on short paths and it is versatile in its applicability. It can be used (i) during testing to perform user-defined hidden-delay-fault test, (ii) for reliability degradation estimation due to process, environmental variations and ageing, and (iii) in security to detect the insertion of Trojan horses that alter the path delay.
Keywords: Hidden-delay-fault, Monitor, Test, Reliability, Security.
