Power Delivery Pathfinding for Emerging Die-to-Wafer Integration Technology
Andrew B. Kahng1,2,a, Seokhyeong Kang3, Seungwon Kim4, Kambiz Samadi5 and Bangqi Xu2,b
1CSE Department, UC San Diego, La Jolla, CA, USA
aabk@ucsd.edu
2ECE Department, UC San Diego, La Jolla, CA, USA
bbangqixu@ucsd.edu
3EE Department, POSTECH, South Korea
shkang@postech.ac.kr
4EE Department, UNIST, South Korea
kskyh002@unist.ac.kr
5Qualcomm Technologies, Inc., San Diego, CA, USA
ksamadi@qti.qualcomm.com
ABSTRACT
In advanced technology nodes, emerging die-towafer (D2W) integration technology is a promising “More Than Moore” lever for continued scaling of system capability and value. In D2W 3D IC implementation, the power delivery network (PDN) is crucial to meeting design specifications. However, determining the optimal PDN design is nontrivial. On the one hand, to meet the IR drop requirement, denser power mesh is desired. On the other hand, to meet the timing requirement for a high-utilization design, more routing resource should be available for signal routing. Moreover, additional competition between signal routing and power routing is caused by intertier vertical interconnects in 3D IC. In this paper, we propose a power delivery pathfinding methodology for emerging die-towafer integration, which seeks to identify an optimal or nearoptimal PDN for a given design and PDN specification. Our pathfinding methodology exploits models for routability and worst IR drop, which helps reduce iterations between PDN design and circuit design in 3D IC implementation. We present validations with real design examples and a 28nm foundry technology.
