Error-Shielded Register Renaming Sub-system for a Dynamically Scheduled Out-of-Order Core

Ron Gabor1, Yiannakis Sazeides2, Arkady Bramnik1, Alexandros Andreou2, Chrysostomos Nicopoulos2, Karyofyllis Patsidis3, Dimitris Konstantinou3 and Giorgos Dimitrakopoulos3
1Intel Israel Design Center, Haifa, Israel
2University of Cyprus, Nicosia, Cyprus
3Democritus University of Thrace, Xanthi, Greece

ABSTRACT


Emerging mission-critical and functional safety applications require high-performance processors that meet strict reliability requirements against random hardware failures. These requirements touch even sub-systems within the core that, so far, may have been considered as low-significance contributors to the processor failure rate. This paper identifies the register renaming sub-system of an out-of-order core as a prime example of where cost-efficient and non-intrusive protection can enable future processors to meet their reliability goals. We propose two hardware schemes that guard against failures in the register renaming sub-system of a core: a technique for the detection of random hardware errors in the physical register identifiers, and a method to recover from the detected errors.

Keywords: Register renaming, Micro-architectural dependability, Mission-critical, Functional safety.



Full Text (PDF)