Design and Evaluation of SmallFloat SIMD extensions to the RISC-V ISA
Giuseppe Tagliavini1,a, Stefan Mach2,d, Davide Rossi1,b, Andrea Marongiu3 and Luca Benini1,2,c,e
1DEI, University of Bologna, Italy
agiuseppe.tagliavini@unibo.it
bdavide.rossi@unibo.it
cluca.benini@unibo.it
2IIS, ETH Zurich, Switzerland
dsmach@iis.ee.ethz.ch
eluca.beninig@iis.ee.ethz.ch
3DISI, University of Bologna, Italy
a.marongiu@unibo.it
ABSTRACT
RISC-V is an open-source instruction set architecture (ISA) with a modular design consisting of a mandatory base part plus optional extensions. The RISC-V 32IMFC ISA configuration has been widely adopted for the design of newgeneration, low-power processors. Motivated by the important energy savings that smaller-than-32-bit FP types have enabled in several application domains and related compute platforms, some recent studies have published encouraging early results for their adoption in RISC-V processors. In this paper we introduce a set of ISA extensions for RISC-V 32IMFC, supporting scalar and SIMD operations (fitting the 32-bit register size) for 8-bit and two 16-bit FP types. The proposed extensions are enabled by exposing the new FP types to the standard C/C++ type system and an implementation for the RISC-V GCC compiler is presented. As a further, novel contribution, we extensively characterize the performance and energy savings achievable with the proposed extensions. On average, experimental results show that their adoption provide benefits in terms of performance (1:64× speedup for 16-bit and 2:18× for 8-bit types) and energy consumption (30% saving for 16-bit and 50% for 8-bit types). We also illustrate an approach based on automatic precision tuning to make effective use of the new FP types.
