Adaptive Word Reordering for Low-Power Inter-Chip Communication
Eleni Maragkoudaki1,a, Przemyslaw Mroszczyk2 and Vasilis F. Pavlidis1,b
1Advanced Processor Technologies Group, School of Computer Science, University of Manchester
aeleni.maragkoudaki@manchester.ac.uk
bpavlidis@cs.man.ac.uk
2Qualcomm, Cork, Ireland
przemyslaw.mroszczyk.23@gmail.com
ABSTRACT
The energy for data transfer has an increasing effect on the total system energy as technology scales, often overtaking computation energy. To reduce the power of interchip interconnects, an adaptive encoding scheme called Adaptive Word Reordering (AWR) is proposed that effectively decreases the number of signal transitions, leading to a significant power reduction. AWR outperforms other adaptive encoding schemes in terms of decrease in transitions, yielding up to 73% reduction in switching. Furthermore, complex bit transition computations are represented as delays in the time domain to limit the power overhead due to encoding. The saved power outweighs the overhead beyond a moderate wire length where the I/O voltage is assumed equal to the core voltage. For a typical I/O voltage, the decrease in power is significant reaching 23% at just 1 mm.
Keywords: Interconnects, Inter-chip communication, Encoding, Low power, Adaptive word reordering.
