A Fine-Grained Soft Error Resilient Architecture under Power Considerations
Sajjad Hussain1,a, Muhammad Shafique2 and Jörg Henkel1,b
1Chair for Embedded Systems (CES), Karlsruhe Institute of Technology (KIT), Germany
asajjad.hussain@kit.edu
bhenkel@kit.edu
2Department of Computer Engineering Vienna University of Technology, Austria
muhammad.shafique@tuwien.ac.at
ABSTRACT
Besides the limited power budgets and the darksilicon issue, soft error is one of the most critical reliability issues in computing systems fabricated using nano-scale devices. During the execution, different applications have varying performance, power/energy consumption and vulnerability properties. Different trade-offs can be devised to provide required resiliency within the allowed power constraints. To exploit this behavior, we propose a novel soft error resilient architecture and the corresponding run-time system that enables power-aware finegrained resiliency for different processor components. It selectively determines the reliability state of various components, such that the overall application reliability is improved under a given power budget. Our architecture saves power up to 16% and reliability degradation up to 11% compared to state-of-the-art techniques.
