HCFTL: A Locality-Aware Page-Level Flash Translation Layer

Hao Chen1,a, Cheng Li1,2,b, Yubiao Pan3, Min Lyu1,2,c, Yongkun Li1,2,d and Yinlong Xu1,2,e
1School of Computer Science and Technology, University of Science and Technology of China, Hefei, China
acighao@mail.ustc.edu.cn
2Anhui Province Key Laboratory of High Performance Computing (USTC), Hefei, China
bchengli7@ustc.edu.cn
cykli@ustc.edu.cn
dlvmin05@ustc.edu.cn
eylxu@ustc.edu.cn
3School of Computer Science and Technology, Huaqiao University, Xiamen, China
panyubiao@hqu.edu.cn

ABSTRACT


The increasing capacity of SSDs requires a large amount of built-in DRAM to hold the mapping information of logical-to-physical address translation. Due to the limited size of DRAM, existing FTL schemes selectively keep some active mapping entries in a Cached Mapping Table (CMT) in DRAM, while storing the entire mapping table on flash. To improve the CMT hit ratio with limited cache space on SSDs, in this paper, we propose a novel FTL, a hot-clusterity FTL (HCFTL) that clusters mapping entries recently evicted from the cache into dynamic translation pages (DTPs). Given the temporal localities that those hot entries are likely to be visited in near future, loading DTPs will increase the CMT hit ratio and thus improve the FTL performance. Furthermore, we introduce an index structure to speedup the lookup of mapping entries in DTPs. Our experiments show that HCFTL can improve the CMT hit ratio by up to 41.1% and decrease the system response time by up to 33.3%, compared to state-of-the-art FTL schemes.



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