Fourℚ on ASIC: Breaking Speed Records for Elliptic Curve Scalar Multiplication
Hiromitsu Awanoa and Makoto Ikedab
VLSI Design and Education Center, The University of Tokyo, Tokyo, Japan
aawano@vdec.u-tokyo.ac.jp
bikeda@silicon.u-tokyo.ac.jp
ABSTRACT
An ASIC cryptoprocessor for scalar multiplication (SM) on Fourℚ is proposed. By exploiting Karatsuba multiplication and lazy reduction techniques, the arithmetic units of the proposed processor are tailored for operations over quadratic extension field (𝔽p2 ). We also propose an automated instruction scheduling methodology based on a combinatorial optimization solver to fully exploit the available instructionlevel parallelism. With the proposed processor fabricated by using a 65nm silicon-on-thin-box (SOTB) CMOS process, we demonstrate that an SM can be computed in 10.1 µs when a typical operating voltage of 1.20V is applied, which corresponds to 3.66×acceleration compared to the conventional P-256 curve SM accelerator implemented on an ASIC platform and is the fastest ever reported. We also demonstrate that by lowering the supply voltage down to 0.32V, the lowest ever reported energy consumption of 0.327 µJ/SM is achieved.
