Wafer-Level Adaptive Vmin Calibration Seed Forecasting
Constantinos Xanthopoulos1, Deepika Neethirajan1, Sirish Boddikurapati2, Amit Nahar2 and Yiorgos Makris1
1Department of Electrical and Computer Engineering, The University of Texas at Dallas, Richardson, TX USA
2Texas Instruments Inc., 12500 TI Boulevard, MS 8741, Dallas, TX USA
ABSTRACT
To combat the effects of process variation in modern, high-performance integrated Circuits (ICs), various postmanufacturing calibrations are typically performed. These calibrations aim to bring each device within its specification limits and ensure that it abides by current technology standards. Moreover, with the increasing popularity of mobile devices that usually depend on finite energy sources, power consumption has been introduced as an additional constraint. As a result, post-silicon calibration is often performed to identify the optimal operating voltage (Vmin) of a given Integrated Circuit. This calibration is time-consuming, as it requires the device to be tested in a wide range of voltage inputs across a large number of tests. In this work, we propose a machine learning-based methodology for reducing the cost of performing the Vmin calibration search, by identifying the optimal wafer-level search parameters. The effectiveness of the proposed methodology is demonstrated on an industrial dataset.
Keywords: Post-silicon calibration, Adaptive test, Test-cost reduction.
