PATCH: Process-Variation-Resilient Space Allocation for Open-Channel SSD with 3D Flash
Jing Chen1, Yi Wang1,a, Amelie Chi Zhou1,b, Rui Mao1,c and Tao Li2
1College of Computer Science and Software Engineering, Shenzhen University, Shenzhen, China
ayiwang@szu.edu.cn
bchi.zhou@szu.edu.cn
cmao@szu.edu.cn
2Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA
taoli@ece.ufl.edu
ABSTRACT
Advanced three-dimensional (3D) flash memory adopts charge-trap technology that can effectively improve the bit density and reduce the coupling effect. Despite these advantages, 3D charge-trap flash brings a number of new challenges. First, current etching process is unable to manufacture perfect channels with identical feature size. Second, the cell current in 3D chargetrap flash is only 20% compared to planar flash memory, making it difficult to give a reliable sensing margin. These issues are affected by process variation, and they pose threats to the integrity of data stored in 3D charge-trap flash.
This paper presents PATCH, a process-variation-resilient space allocation scheme for open-channel SSD with 3D charge-trap flash memory. PATCH is a novel hardware and file system interface that can transparently allocate physical space in the presence of process variation. PATCH utilizes the rich functionalities provided by the system infrastructure of open-channel SSD to reduce the uncorrectable bit errors. We demonstrate the viability of the proposed technique using a set of extensive experiments. Experimental results show that PATCH can effectively enhance the reliability with negligible extra erase operations in comparison with representative schemes.
Keywords: Three-dimensional flash memory, Process variation, Open-channel SSD, Charge-trap flash, Space allocation.
