SDCNN: An Efficient Sparse Deconvolutional Neural Network Accelerator on FPGA
Jung-Woo Changa, Keon-Woo Kangb and Suk-Ju Kangc
Dept. of Electronic Engineering, Sogang University, Seoul, South Korea
azwzang91@sogang.ac.kr
bkkw0526@sogang.ac.kr
csjkang@sogang.ac.kr
ABSTRACT
Generative adversarial networks (GANs) have shown excellent performance in image generation applications. GAN typically uses a new type of neural network called deconvolutional neural network (DCNN). To implement DCNN in hardware, the state-of-the-art DCNN accelerator optimizes the dataflow using DCNN-to-CNN conversion method. However, this method still requires high computational complexity because the number of feature maps is increased when converted from DCNN to CNN. Recently, pruning has been recognized as an effective solution to reduce the high computational complexity and huge network model size. In this paper, we propose a novel sparse DCNN accelerator (SDCNN) combining these approaches on FPGA. First, we propose a novel dataflow suitable for the sparse DCNN acceleration by loop transformation. Then, we introduce a four stage pipeline for generating the SDCNN model. Finally, we propose an efficient architecture based on SDCNN dataflow. Experimental results on DCGAN show that SDCNN achieves up to 2.63 times speedup over the state-of-the-art DCNN accelerator.
