Empirical Evaluation of IC3-Based Model Checking Techniques on Verilog RTL Designs
Aman Goela and Karem Sakallahb
University of Michigan, Ann Arbor
aamangoel@umich.edu
bkarem@umich.edu
ABSTRACT
IC3-based algorithms have emerged as effective scalable approaches for hardware model checking. In this paper we evaluate six implementations of IC3-based model checkers on a diverse set of publicly-available and proprietary industrial Verilog RTL designs. Four of the six verifiers we examined operate at the bit level and two employ abstraction to take advantage of word-level RTL semantics. Overall, the word-level verifier employing data abstraction outperformed the others, especially on the large industrial designs. The analysis helped us identify several key insights on the techniques underlying these tools, their strengths and weaknesses, differences and commonalities, and opportunities for improvement.
