Detailed Placement for IR Drop Mitigation by Power Staple Insertion in Sub-10nm VLSI
Sun ik Heo1, Andrew B. Kahng2,a, Minsoo Kim2,b, Lutong Wang2,c and Chutong Yang2,d
1Samsung Electronics Co., Ltd., Hwaseong-si, Gyeonggi-do, South Korea
sunik.heo@samsung.com
2UC San Diego, La Jolla, CA, USA
aabk@ucsd.edu
bmik226@ucsd.edu
cluw002@ucsd.edu
dchy136@ucsd.edu
ABSTRACT
Power Delivery Network (PDN) is one of the most challenging topics in modern VLSI design. Due to aggressive technology node scaling, resistance of back-end-of-line (BEOL) layers increases dramatically in sub-10nm VLSI, causing high supply voltage (IR) drop. To solve this problem, pre-placed or postplaced power staples are inserted in pin-access layers to connect adjacent power rails and reduce PDN resistance, at the cost of reduced routing flexibility, or reduced power staple insertion opportunity. In this work, we propose dynamic programmingbased single-row and double-row detailed placement optimizations to maximize the power staple insertion in a post-placement flow. We further propose metaheuristics to improve the quality of result. Compared to the traditional post-placement flow, we achieve up to 13.2% (10mV ) reduction in IR drop, with almost no WNS degradation.
