Methodology for Application-Dependent Degradation Analysis of Memory Timing
Daniël Kraak1,a, Innocent Agbo1,b, Mottaqiallah Taouil1,c, Said Hamdioui1,d, Pieter Weckx2,3,e, Stefan Cosemans2 and Francky Catthoor2,3,f
1Delft University of Technology, The Netherlands
aD.H.P.Kraak@tudelft.nl
bI.O.Agbo@tudelft.nl
cM.Taouil@tudelft.nl
dS.Hamdioui@tudelft.nl
2imec vzw., Kapeldreef, Leuven, Belgium
3Katholieke Universiteit Leuven, ESAT, Belgium
ePieter.Weckx@imec.be
fFrancky.Catthoor@imec.be
ABSTRACT
Memory designs typically contain design margins to compensate for aging. As aging impact becomes more severe with technology scaling, it is crucial to accurately predict such impact to prevent overestimation or underestimation of the margins. This paper proposes a methodology to accurately and efficiently analyze the impact of aging on the memory’s digital logic (e.g., timing circuit and address decoder) while considering realistic workloads extracted from applications. To demonstrate the superiority of the methodology, we analyzed the degradation of the L1 data and instruction caches for an ARM v8-a processor using both our methodology as well as the state-of-the-art methods. The results show that the existing methods may significantly overor underestimate the impact (e.g., the decoder margin up to 221% and the access time up to 20%) as compared with the proposed scheme. In addition, the results show that in general the instruction cache has the highest degradation. For example, its access time degrades up to 9% and its decoder margin up to 44%.
Keywords: Memory, Aging, Timing, Address Decoder.
