Design of Reliable DNN Accelerator with Un-reliable ReRAM
Yun Longa, Xueyuan Sheb and Saibal Mukhopadhyayc
School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, USA
ayunlong@gatech.edu
bxshe6@gatech.edu
csaibal.mukhopadhyay@gatech.edu
ABSTRACT
This paper presents an algorithmic approach to design reliable ReRAM based Processing-in-Memory (PIM) architecture for Deep Neural Network (DNN) acceleration under intrinsic stochastic behavior of ReRAM devices. We employ the dynamical fixed point (DFP) data representation format to adaptively change the decimal point location based on the data range, minimizing the unused most significant bits (MSBs). Further, we propose a device variability aware (DVA) training methodology where stochastic noise is added to the parameters during training to enhance the robustness of network to the parameter’s variation. Simulations indicate that, on average, the proposed algorithms improve the computing accuracy by more than 20% considering various benchmark DNNs (convolutional and recurrent). Moreover, the proposed approach enhances robustness of the DNN to noisy input data.
