Common-Mode Failure Mitigation: Increasing Diversity through High-Level Synthesis
Farah Naz Taher1,a, Matthew Joslin1,b, Anjana Balachandran2, Zhiqi Zhu1,c and Benjamin Carrion Schafer1,d
1The University of Texas at Dallas
afarah.taher@utdallas.edu
bmatthew.josling@utdallas.edu
czhiqi.zhu@utdallas.edu
dschaferb@utdallas.edu
2The Hong Kong Polytechnic University
anjana.balachandran@polyu.hk
ABSTRACT
Fault tolerance is vital in many domains. One popular way to increase fault-tolerance is through hardware redundancy. However, basic redundancy cannot cope with Common Mode Failures (CMFs). One way to address CMF is through the use of diversity in combination with traditional hardware redundancy. This work proposes an automatic design space exploration (DSE) method to generate optimized redundant hardware accelerators with maximum diversity to protect against CMFs given as a single behavioral description for High-Level Synthesis (HLS). For this purpose, this work exploits one of the main advantages of C-based VLSI design over the traditional RTlevel design based on low-level Hardware Description Languages (HDLs): The ability to generate micro-architectures with unique characteristics from the same behavioral description. Experimental results show that the proposed method provides a significant diversity increment compared to using traditional RTL-based exploration to generate diverse designs.
