GraphS: A Graph Processing Accelerator Leveraging SOT-MRAM
Shaahin Angizi1,a, Jiao Sun2, Wei Zhang2 and Deliang Fan1,b
1Department of Electrical and Computer Engineering, University of Central Florida, Orlando, FL 32816
aangizi@knights.ucf.edu
bdfan@ucf.edu
2Department of Computer Science, University of Central Florida
ABSTRACT
In this work, we present GraphS architecture, which transforms current Spin Orbit Torque Magnetic Random Access Memory (SOT-MRAM) to massively parallel computational units capable of accelerating graph processing applications. GraphS can be leveraged to greatly reduce energy consumption dealing with underlying adjacency matrix computations, eliminating unnecessary off-chip accesses and providing ultra-high internal vbandwidth. The device-to-architecture co-simulation for three social network data-sets indicate roughly 3.6× higher energyefficiency and 5.3× speed-up over recent ReRAM crossbar. It achieves ∼4× higher energy-efficiency and 5.1× speed-up over recent processing-in-DRAM acceleration methods.
