Power and Performance Optimal NoC Design for CPU-GPU Architecture Using Formal Models
Lulwah Alhubaila and Nader Bagherzadehb
University of California, Irvine, California
alalhubai@uci.edu
bnader@uci.edu
ABSTRACT
Heterogeneous computing architectures that fuse both CPU and GPU on the same chip are common nowadays. Using homogeneous interconnect for such heterogeneous processors each with different network demands can result in performance degradation. In this paper, we focused on designing a heterogeneous mesh-style network-on-chip (NoC) to connect heterogeneous CPU-GPU processors. We tackled three problems at once; mapping Processing Elements (PEs) to the routers of the mesh, assigning the number of virtual channels (VC), and assigning the buffer size (BS) for each port of each router in the NoC. By relying on formal models, we developed a method based on Strength Pareto Evolutionary Algorithm2 (SPEA2) to obtain the Pareto optimal set that optimizes communication performance and power consumption of the NoC. By validating our method on a full-system simulator, results show that the NoC performance can be improved by 17% while minimizing the power consumption by at least 2.3x and maintaining the overall system performance.
Keywords: Heterogeneous architecture, Network-on-Chip, Optimization, Performance, Power, Evolutionary algorithm.
