Time-division Multiplexing Automata Processor
Jintao Yua, Hoang Anh Du Nguyenb, Muath Abu Lebdehc, Mottaqiallah Taouild and Said Hamdiouie
Laboratory of Computer Engineering, Delft University of Technology, Delft, the Netherlands
aJ.Yu-1@tudelft.nl
bH.A.DuNguyen@tudelft.nl
cM.F.M.AbuLebdeh@tudelft.nl
dM.Taouil@tudelft.nl
eS.Hamdioui@tudelft.nl
ABSTRACT
Automata Processor (AP) is a special implementation of non-deterministic finite automata that performs pattern matching by exploring parallel state transitions. The implementation typically contains a hierarchical switching network, causing long latency. This paper proposes a methodology to split such a hierarchical switching network into multiple pipelined stages, making it possible to process several input sequences in parallel by using time-division multiplexing. We use a new resistive RAM based AP (instead of known DRAM or SRAM based) to illustrate the potential of our method. The experimental results show that our approach increases the throughput by almost a factor of 2 at a cost of marginal area overhead.
Keywords: Time-devision multiplexing, Automata, Parallel processing.
