Effect of Device Variation on Mapping Binary Neural Network to Memristor Crossbar Array
Wooseok Yia, Yulhwa Kimb and Jae-Joon Kimc
Creative IT Engineering, Pohang University of Science and Technology (POSTECH), Pohang, Republic of Korea
awooseok.yi@postech.ac.kr
byulhwa.kim@postech.ac.kr
cjaejoon@postech.ac.kr
ABSTRACT
In memristor crossbar array (MCA)-based neural network hardware, it is generally assumed that entire wordlines (WLs) are simultaneously enabled for parallel matrix-vector multiplication (MxV) operation. However, the error probability of MxV in a memristor crossbar array (MCA) increases as the resistance ratio (R-ratio) of a memristor decreases and the resistance variation and the number of simultaneously activated WLs increase. In this paper, we analyze the effect of R-ratio and variation of memristor devices on read sense margin and inference accuracy of MCA-based Binary Neural Network (BNN) hardware. We first show that only a limited number of WLs should be enabled to ensure correct MxV output when the R-ratio is small. On the other hand, we also show that, if the resistance variation becomes higher than a certain level, simultaneous activation of large number of WLs produces the higher accuracy even when R-ratio is small. Based on the analysis, we propose the Accuracy Estimation (AE) factor to find the optimal number of word lines that are simultaneously activated.
