SiPterposer: A Fault-Tolerant Substrate for Flexible System-in-Package Design
Pete Ehretta, Todd Austinb and Valeria Bertaccoc
University of Michigan, Ann Arbor
awpehrett@umich.edu
baustin@umich.edu
cvaleria@umich.edu
ABSTRACT
As Moore’s Law scaling slows down, specialized heterogeneous designs are needed to sustain computing performance improvements. Unfortunately, the non-recurring engineering (NRE) costs of chip design—designing interconnects, creating masks, etc.—are often prohibitive. Chiplet-based disintegrated design solutions could address these economic issues, but current technologies lack the flexibility to express a rich variety of designs without redesigning the communication substrate. Moreover, as the number of chiplets increases, yield suffers due to 2.5D assembly defects. This work addresses these problems by presenting a flexible communication fabric that supports construction of arbitrary network topologies and provides robust fault-tolerance, demonstrating near-100% chip assembly yield at typical bonding defect rates. We achieve these goals with less than 3% additional power and zero exposed latency overhead for various real-world applications running on an example SiP.
