Scratchpad Memories with Ownership
Martin Schoeberla, Tórur Biskopstø Strømb, Oktay Barisc and Jens Sparsød
Technical University of Denmark
amasca@dtu.dk
btbst@dtu.dk
cokba@dtu.dk
djspa@dtu.dk
ABSTRACT
A multicore processor for real-time systems needs a time-predictable way to communicate data between different threads running on different cores. Standard multicore processors support data sharing with shared main memory backed up by caches and cache coherence protocol. This sharing solution is hardly time predictable nor does it scale to more than a few cores.
This paper presents a shared scratchpad memory (SPM) for time-predictable communication between cores. The base architecture uses time-division multiplexing for the arbitration of the access to the shared SPM. This allows the timing of programs executing on different cores to be completely independent of each other. We extend this architecture by the notion of ownership. A core can own the SPM. Having exclusive access to the SPM reduces the access time to a single clock cycle. The ownership of the SPM can then be transferred to a different core, implementing low latency communication of bulk data. As an extension, we propose to organize this memory as a pool of SPMs that can be owned by different cores and transferred as needed. We evaluate the proposed architecture within the T-CREST multicore architecture.
Keywords: Scratchpad Memory, Multicore, Real-Time Systems.
