Timing Violation Induced Faults in Multi-Tenant FPGAs
Dina Mahmouda and Mirjana Stojilovićb
École Polytechnique Fédérale de Lausanne (EPFL), Lausanne, Switzerland
adina.mahmoud@epfl.ch
bmirjana.stojilovic@epfl.ch
ABSTRACT
FPGAs have made their way into the cloud, allowing users to gain remote access to the state-of-the-art reconfigurable fabric and implement their custom accelerators. Since FPGAs are large enough to accommodate multiple independent designs, the multi-tenant user scenario may soon be prevalent in cloud computing environments. However, shared use of an FPGA raises security concerns. Recently discovered hardware Trojans for use in multi-tenant FPGA settings target denial-of-service attacks, power side-channel attacks, and crosstalk side-channel attacks. In this work, we present an attack method for causing timingconstraints violation in the multi-tenant FPGA setting. This type of attack is very dangerous as the consequences of timing faults are temporary errors, which are often impossible to notice. We demonstrate the attack on a set of self-timed true random number generators (STRNGs), frequently used in cryptographic applications. When the attack is launched, the STRNG outputs become biased and fail randomness tests. However, after the attack, STRNGs recover and continue generating random bits.
Keywords: FPGA, cloud, Multi-tenancy, Security, Random number generator, Timing fault, Voltage drop.
