Realizing Reproducible and Reusable Parallel Floating Random Walk Solvers for Practical Usage
Mingye Song1,a, Zhezhao Xu1,b, Wenjian Yu1,c and Lei Yin2
1Tsinghua University, Beijing, China
asongmy16@mails.tsinghua.edu.cn
bzhezhaoxu@gmail.com
cyu-wj@tsinghua.edu.cn
2ANSYS, Inc., USA
lei.yin@ansys.com
ABSTRACT
Capacitance extraction or simulation has become a challenging problem in the computer-aided design of integrated circuits (ICs), flat panel display, etc. Due to its scalability and reliability, the parallel floating random walk (FRW) based capacitance solver is widely used. In practice, the parallel FRW algorithms involve an issue of reproducibility and may consume a lot of time in the scenario requesting high accuracy. To relieve these issues, techniques are developed in this paper to enhance the reproducibility and reusability of the parallel FRW based simulation. With them we ensure that same result is reproduced while rerunning the parallel FRW solver with same setting. A “jump start” feature is also implemented to reduce the total runtime of simulating same structure with multiple accuracy criteria. Experiments on shared-memory and distributed-memory platforms have validated the effectiveness of the presented techniques. Compared with a synchronization based approach ensuring the reproducibility, the proposed technique with static workload allocation can brings 4.8X more parallel speedup while sacrificing nothing.
Keywords: Capacitance extraction/simulation, Floating random walk (FRW) method, High-performance computing, Reproducibility.
