Predicting Critical Warps in Near-Threshold GPGPU Applications using a Dynamic Choke Point Analysis
Sourav Sanyala, Prabal Basub, Aatreyi Balc, Sanghamitra Royd and Koushik Chakrabortye
USU BRIDGE LAB, Electrical and Computer Engineering, Utah State University
asourav.sanyal@aggiemail.usu.edu
bprabalb@aggiemail.usu.edu
caatreyi.bal@aggiemail.usu.edu
dsanghamitra.roy@usu.edu
ekoushik.chakraborty@usu.edu
ABSTRACT
General purpose graphics processing units (GP-GPU) can significantly improve the power consumption at the NTC operating region. However, process variation (PV) can drastically reduce its performance. In this paper, we examine choke points-a unique device-level characteristic of PV at NTC-that can exacerbate the warp criticality problem. We show that themodernwarp schedulers cannot tackle the choke point induced critical warps in an NTC GPU. We propose Warp Latency Booster, a circuit-architectural solution to dynamically predict the critical warps and accelerate them in their respective execution units. Our best scheme achieves an average improvement of∼32%and∼41%in performance, and∼21%and∼19%in energy-efficiency, respectively, over two state-of-the-art warp schedulers.
