CORN: In-Buffer Computing for Binary Neural Network
Liang Chang1,2, Xin Ma2, Zhaohao Wang1, Youguang Zhang1, Weisheng Zhao1 and Yuan Xie2
1Fert Beijing Research Institute, BDBC, School of Electronic and Information Engineering, Beihang University
2Electrical and Computer Engineering, University of California, Santa Barbara
ABSTRACT
Binary Neural Networks (BNNs) have obtained great attention since they reduce memory usage and power consumption as well as achieve a satisfying recognition accuracy on Image Classification. In particular to the computation of BNNs, the multiply-accumulate operations of convolution-layer are replaced with the bit-wise operations (XNOR and pop-count). Such bitwise operations are well suited for the hardware accelerator such as in-memory computing (IMC). However, an additional digital processing unit (DPU) is required for the pop-count operation, which induces considerable data movement between the Process Engines (PEs) and data buffers reducing the efficiency of the IMC. In this paper, we present a BNN computing accelerator, namely CORN, which consists of a Spin-Orbit-Torque Magnetic RAM (SOT-MRAM) based data buffer to perform the majority operation (to replace the pop-count process) with the SOTMRAM- based IMC to accelerate the computing of BNNs. CORN can naturally implement the XNOR operation in the NVM memory array, and feed results to the computing data buffer for the majority write operation. Such a design removes the popcounter implemented by the DPU and reduces data movement between the data buffer and the memory array. Based on the evaluation results, CORN achieves 61% and 14% power saving with 1:74× and 2:12× speedup, compared to the FPGA and DPU based IMC architecture, respectively.
Keywords: MRAM, Spin Orbit Torque, Binary Neural Networks, Write Operation, Preset-XNOR.
