From Device to System: Cross-layer Design Exploration of Racetrack Memory
Guangyu Sun1,a, Chao Zhang1, Hehe Li2, Yue Zhang4, Weiqi Zhang1, Yizi Gu2, Yinan Sun2, J.-O. Klein4, D. Ravelosona4, Yongpan Liu2,b, Weisheng Zhao3,4,c and Huazhong Yang2
1CECA, Peking University, Beijing, China.
2EE Department, Tsinghua University, Beijing, China.
3Spintronics Interdisciplinary Center, Beihang University, Beijing, China.
4Institut d'lectronique Fondamentale, Univ. Paris-Sud/UMR 8622 CNRS, Orsay, France
Recently, Racetrack Memory (RM) has attracted more and more attention of memory researchers because it has advantages of ultra-high storage density, fast access speed, and non-volatility. Prior research has demonstrated that RM has potential to replace SRAM for large capacity on-chip memory design. At the same time, it also addressed that the design space exploration of RM could be more complicated compared to traditional on-chip memory technologies for several reasons. First, a single RM cell introduces more device level design parameters. Second, considering these device-level design factors, the layout exploration of a RM array demonstrates trade-off among area, performance, and power consumption of RM circuit level design. Third, in the architecture level, the unique “shift” operation results in an extra dimension for design exploration. In this paper, we will review all these design issues in different layers and try to reveal the relationship among them. The experimental results demonstrate that cross-layer design exploration is necessary for racetrack memory. In addition, a system level case study of using RM in a sensor node is presented to demonstrate its advantages over SRAM or STT-RAM.
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